Speculative parallelization needs rigor

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

A new fast PWM modulation strategy for power electric converter based on finite set state machine theory

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept of a semi-synchronous FSM that combines the benefits of both synchronous and asynchronous state machines. The result is a FSM which runs at high clock frequency, consumes very little power and can be implemented, verified and tested as a synchronous FSM. This concept has been used to design a PFM FSM in a field programmable gate array (FPGA) and in a 65 nm CMOS technology.

(Self-)reconfigurable finite state machine (FSM) had been introduced as a formal model to implement the sequential circuit which can be reconfigured during the operation. The reconfiguration is initiated by the external events or by the controller that generates the reconfiguration transitions. In this paper, we optimize the number of reconfiguration transitions required to reconfigure a given FSM into a new target FSM. A serious limitation of previously proposed techniques is that they depend on the number of essential transitions which are the different transitions between a given and a target FSMs. In this paper, we propose a new technique based on FSM decomposition to decompose a given and target FSMs into two sub machines. A part of essential transitions is implemented as a single decomposed submachine with the same functionality in two decomposed FSMs. This submachine is inactive and has no effect in the normal operation but reduces the number of essential transitions during the reconfiguration. We give a decomposition strategy, realize the proper hardware, and provide a set of experimental results that shows the reconfiguration transitions can be substantially reduced, in some cases up to 54%

In this paper we outline a theory for the environment-modeling problem , the problem of abstracting component finite state machines (FSMs)bordering a particular FSM of interest within a network of interacting FSMs. The goal is to lay a theoretical foundation for the automatic state reduction of large FSM networks. We feel this is a prerequisite for the efficient use of many verification techniques. We focus on computing conditions for the safe removal of a component FSM in a FSM network, where removal is safe if it preserves a certain well-defined trace equivalence. We present an optimized algorithm for determining language universality of a FSM, as well as determining independence of a FSM from those of its inputs connected to outputs of neighboring FSMs. These two properties, input independence and language universality, provide the necessary and sufficient conditions for safe removal. In addition, we show how simulation relations can be utilized, both to reduce the cost of computing safe removal and to create an appropriate abstract FSM when safe removal is not possible.

Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test generation, and fault coverage. Finite state machines (FSMs) are commonly used for specifying controllers. FSMs may have shortcomings in modeling complex systems. With the introduction of X-machines, complex systems can be modeled at higher levels of abstraction. An X-machine can be converted into an FSM while preserving the level of abstraction. The fault coverage of a test sequence for an FSM specification provides a confidence level. We propose a fault coverage metric for an FSM specification based on the transition fault model, and using this metric, we derive the coverage of a test sequence. The article also presents a method which generates short test sequences that meet a specific coverage level and then extends this metric to determine the coverage of a test sequence for an FSM driven by an FSM network. We applied our FSM verification technique to a real-life FSM, namely, the fibre channel arbitrated loop port state machine, used in the field of storage area networks.

State space exploration is often used to prove properties about sequential behavior of Finite State Machines (FSMs). For example, equivalence of two machines is proved by analyzing the reachable state set of their product machine. Nevertheless, reachability analysis is infeasible on large practical examples. Combinational verification is far less expensive, but on the other hand its application is limited to combinational circuits, or particular design schemes. Finally, approximate techniques imply sufficient, not strictly necessary conditions. The purpose of this paper is to extend the applicability of purely combinational checks. This is generally achieved through state minimization, partitioning, and re-encoding the FSMs to factor out their differences. We focus on re-encoding. In particular, we present an incremental approach to re-encoding for verification that transforms the product machine traversal into a combinational verification in the best case, and into a computationally simpler product machine traversal in the general case. Experimental results demonstrate the effectiveness of this technique on medium-large circuits where other techniques may fail.

In this work, an efficient technique of clock and power gating is concurrently introduced in finite state machines (FSM) with a view to minimising the overall power dissipation. The proposed power gating concept works on the principle of shutting down the power supply to the FSM during periods of inactivity. The extraction of the inactivity criteria is based on the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating, on the other hand, disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The idea of implementing the gating in both the state logic as well as output logic is introduced in this work. The proposed approach has been introduced in three benchmark FSM circuits, simulated and synthesised in Cadence digital design tool. The results indicate a maximum of 73% total power savings (dynamic and static) with an average penalty of 27% area (approx.).

Model-based testing has recently been receiving more and more attention in Microsoft’s product groups. Typically, the models are required to be finite state machines (FSMs) because there is well-known algorithmic support for test case generation for FSMs. The direct FSM based modeling approach has its limitations though. Most noticeably, the FSM model for a particular testing problem may not be the most natural one to describe the implementation under test. This motivated us to study the problem of algorithmic generation of an FSM from a given AsmL spec1. We have developed a pragmatic test case generation tool where the FSM generation algorithm is used and has been extended in several ways.

The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs.This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

In this paper we consider one of the classical finite state machine (FSM) model modifications FSM with time-outs (or timed FSM). In this model in addition to the ordinary transitions under inputs there are transitions under time-outs when no input is applying. The behavior of many modern systems includes time-outs, for example, mobile phones, etc. In the past few years some work have been carried out on studying different relations between timed FSMs. Non-separability relation is very attractive for non-deterministic classical FSMs and FSMs with time-outs course for this relation we don’t need «all weather conditions» while testing. In this paper we present and compare two approaches for building a separating sequence for two separable FSMs with time-outs. One of them is using a conversion to classical FSMs, while another one is dealing directly with timed FSMs.

Synthesis of finite state machines for improved state verification

This paper presents a VHDL-based methodology to design Self-Checking (SC) Finite State Machines (FSM). The methodology provides a library of pre-designed, parameterized concurrent error-detection (CED) modules as well as a VHDL code template that allow easily creation of synthesizable highlevel description of the SC FSM with minor additional design development time. The template offers selection of error-detecting schemes that will be used for encoding output data and states of the FSM. The generated SC FSM description can be simulated and synthesized with commercial tools. Effectiveness of the methodology is evaluated on a set of benchmark FSMs.

Finite State Machines (FSMs) are widely used for analysis and synthesis of digital components of control systems. In order to take into account time aspects, timed FSMs are considered. In this paper, we address the problem of deriving a parallel composition of two types of Timed Finite State Machines (TFSM), namely, FSMs with timeouts and FSMs with timed guards. These two TFSM types are not interchangeable and are particular cases of a more general TFSM model that has timeouts and timed guards. We also assume that all of considered TFSMs have output delays (output timeouts). When considering the parallel composition, component FSMs work in the dialog and the composition produces an external output when interaction between components is finished. In this work, it is shown that in the general case, unlike classical FSMs, a slow environment and the absence of livelocks are not enough for describing the behavior of a composition by a complete deterministic FSM with a single clock. The latter occurs when inputs can be applied to TFSMs not only at integer time instances but also at rational. A class of systems for which the behavior can be described by a complete deterministic TFSM is specified. Those are systems where both component TFSMs are participating in the dialog when an external input is applied; a sequential composition of TFSMs is a particular case of such composition.