Split frequency high‐voltage driver for dynamic load modulated RF amplifiers

Dynamic load modulation (DLM) is a technique for increasing radio frequency (RF) power amplifier (PA) efficiency when amplifying amplitude modulated signals. It does this by manipulating a tuneable matching network (TMN) between the PA and the antenna in harmony with the envelope of the transmitted signal. The TMN is usually based on varactor diodes, requiring control voltages with up to 100 V peak-to-peak swing. Conventional off-the-shelf op-amps cannot produce a big enough voltage swing at sufficient speed, especially when amplifying modern communications standards like the 3GPP 4G Long Term Evolution (LTE). The discrete current mirror driver amplifier described here capable of producing 50V peak-to-peak voltage swing. When the driver amplifier was combined with a suitable RF PA and TMN, 46.0% DC-to-RF efficiency was achieved at 33.9 dBm output power (POUT) with a 1.4 MHz LTE signal. The adjacent channel power ratio (ACPR) was -40 dBc, confirming that the current mirror amplifier is suitable for LTE use.

A theory for class-J microwave amplifier operation as a function of drive level and fundamental load impedance is derived. Calculations show that, under appropriate operating conditions, it is sufficient to modulate the transistor load reactance to enable high-efficiency operation (>;70%) over a large output power dynamic range (>;10 dB) with high transistor power utilization. Such dynamic load modulation (DLM) networks are an ideal application of continuously tunable varactor technologies. Multiharmonic load-pull measurements are performed on a GaN HEMT and experimentally verify the theory of operation. A demonstrator amplifier using an SiC varactor technology is then designed and characterized by static measurements. The amplifier has a peak power of 38 dBm at 2.08 GHz and maintains efficiencies above 45% over 8 dB of power dynamic range. An analysis of the load network losses is performed to show the potential of the class-J DLM transmitter concept.

In this paper, the high potential of varactor-based dynamic load modulation (DLM) techniques for wideband cellular applications is demonstrated. A systematic design procedure is proposed to ensure high-efficiency wideband performance. It incorporates harmonically tuned power amplifier (PA) concepts and tunable matching techniques in an integrated design. A DLM transmitter at 2.65 GHz with a peak output power of 6 W is designed using the proposed procedure. In order to investigate the wideband performance of the implemented demonstrator, WCDMA signals with scaled bandwidths are employed. The signal peak-to-average ratio is 7 dB and the same for all the experiments. For the 38.4-MHz signal, which has a corresponding channel bandwidth of > 40 MHz, an average power added-efficiency (PAE) of 44%, normalized mean square error (NMSE) of -35 dB, and adjacent channel leakage ratio (ACLR) of -43 dBc are measured.

In this paper, an analytical design space of power amplifiers (PAs) including the Class-A/B/J continuum for dynamic load modulation (DLM) at the current generator plane (CGP) is proposed based on the theory of load modulated (LM) continuous Class-B/J PAs. By introducing a biasing operation factor ρ, the theory of DLM PAs provides an analytical design space for all the operation modes from Class-B/J mode to Class-A mode. The analytical design space of DLM PAs shows that high efficiency is maintained at a large dynamic range of output power back-off (OPBO) with a purely resistive load modulation at the CGP when Class-B/J mode is performed. For deep Class-AB mode, the analytical design space of the DLM PAs shows that a combination of resistive and reactive load modulation at the CGP is used to maintain the high efficiency at the OPBO. The effectiveness of the proposed analytical design space is validated by load-pull measurements of a bare-chip gallium nitride (GaN) device.

A GaN power amplifier is presented with a tunable output matching network, based on varactor diodes which provide a dual functionality. Firstly, they enhance back-off efficiency through dynamic load-modulation (between 0.9–1.0GHz). Secondly, they re-configure the amplifier to operate over additional frequencies (between 0.6–0.9GHz). The prototype PA measured with a 1.4MHz LTE signal, and after optimisation of the drain supply level, delivered 33.7–35.1dBm with 33.2–47.9% efficiency over 0.6–1.08GHz and <−28.2dBc ACPR, without any linearisation. Finally, output power control is demonstrated through simple supply voltage scaling with high efficiency maintained over a 10 dB output power dynamic range.

Dynamic load modulation is proposed to improve the efficiency of an RF power amplifier with discrete supply modulation. A 47.5 dBm, 2.7 GHz power amplifier is realized to show the potential of the method. The amplifier design is based on continuous wave load-pull measurements to determine the optimum load impedances, using the statistics of a 10.2 dB PAPR OFDM signal. The output network contains a single SiC varactor for adaptive output matching. The supply voltage is adjusted by a 2-level supply modulator. Static evaluation of the amplifier shows an improvement in PAE of approximately 9.7 percentage points at 10 dB back-off due to load modulation.

In this letter, we propose a novel simultaneous wireless information and power transfer (SWIPT) scheme, namely the frequency-splitting (FS) SWIPT, which separates the power and data signals in the frequency domain. The proposed FS SWIPT scheme is advantageous in that it can maximize the efficiency of the high power amplifier (HPA) in the transmitter and reduce the harmonic distortion caused by the nonlinearity of the HPA. We design a receiver circuit for the FS SWIPT by using a circulator and filters. We analyze the FS and conventional power-splitting (PS) SWIPT schemes in consideration of the nonlinearity of the HPA. We show that the proposed FS SWIPT greatly outperforms the PS SWIPT in terms of the harvested power and signal-to-noise ratio (SNR).

RF transistors can be found in several present day electronics including mobile radio and telecommunication applications, TV & radio broadcast, avionics, radar and defense communications as well as industrial, scientific, medical (ISM) and broadcast applications. The increasing demands for data anywhere/anytime (mobile internet) requires increased deployment of wireless communication infrastructure. This has pushed upwards across the supply chain (suppliers and customers alike). At the core are RF power amplifiers (PA) with a very costly design, hence important to get it right as rework may not be possible. The assembly of RF power transistors in PA modules is the back-bone of these applications. Such modules are usually generating high power (> 100 watts) with different package outlines and lead configuration. The high power demands excellent thermal management, else product performance and lifetime (reliability) are compromised. As a consequence, the transistors are often packaged in "chunky" S OT outlines, with a cerami c/plastic body and a metal flange. Packaging such RF power modules (or PA) has historically been achieved with bolt down devices, where only the leads of the components were soldered (more akin to manual assembly operations). A thermal compound was used underneath the transistor. High volume assembly is a basic capability (with automation a necessity) to meet industry demand. There are a variety of issues to consider module assembly since there are strong interplay between design, materials and process in order to achieve the desired performance (electrical, thermal, mechanical, and reliability). Due to thermal management requirement, the transistors are normally soldered directly onto the pallet (laminate bonded onto a heat sink) with the leads and SMDs on to the laminate on the pallet. Base on the SOT outline (i.e. gull wing), a cavity or pedestal is required in the pallet with a cut-out in the laminate. Each PA module will be different in i.e. size, weight, materials, number of transistors, board construction with no two modules the same. With such spectra of possibilities in the module design and permutations on assembly processes, the paper outlines and addresses the key issues to consider and approach to achieve robust PA modules assembly. It includes but not limited to substrates, solders, heat sinks, plating, board design and reflow soldering (assembly process flow). Key to achieving the robust assembly process is an iterative approach with feedback at each step in the process including a modeled reflow profiling. In addition, a novel use of Rth (thermal impedance) in combination to acoustic microscopy / x-rays to assess the quality of the soldered interface is presented. The solder volume is key to accommodate manufacturing tolerances and solder joint reliability. Additionally, the issues presented constitute a "toll-box" for PA module assembly, including microwave pallet modules with matched input/output impedance.

An input driver circuit for driving a cascode stage Class F RF Power Amplifier in deep submicron CMOS technology is proposed. The input driver circuit will deliver an improvement to the RF Power Amplifier's efficiency by reducing drain current distortion and provide better breakdown voltage protection for the transistor. The proposed input driver and Class F Power Amplifier are designed using Silterra RF CMOS 0.18μm technology and simulated using Hspice.

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

Power amplifiers are crucial components that significantly influence the linearity and energy efficiency of next-generation communication system radio units. A key challenge in designing power amplifiers is managing high peak-to-average power ratio (PAPR) in order to achieve both high linearity and energy efficiency during back-off conditions. This paper presents simulation and measurement results for a dynamic load modulation power amplifier based on a ferroelectric tunable matching network to operate at 2.5 GHz. Experimental studies on a power amplifier with the tunable output matching network confirm its performance at 8 dB back-off while varying the control voltage applied to the ferroelectric element. Additionally, a bias modulator to adjust the transistor's load in relation to input power was designed. Measurement studies of the dynamic load modulation power amplifier have demonstrated an efficiency of at least 50% at 8 dB back-off and more than 60% at peak power at 2.5 GHz. Furthermore, it was found that the modulator output voltage adjustment function on input power of the bias modulator affects the linearity of the output power. Different bias responses were studied and, as a result, the optimal output voltage response was found. The proposed load modulation power amplifier is promising for operation with high PAPR digital signals.

This paper describes design and analysis of voltage controlled oscillator using NPN Silicon Germanium RF transistor operating in Ku-band frequencies. Novel topology is proposed with tunable active matching filter networks are used as resonators connected to parallel emitters. Resonator contains varactor diodes to provide voltage controlled frequency tuning. Series LC network connected at the base of device helps in increasing S11 and S22 >1 further leading to enough negative resistance at input and output ports. Analysis shows that it provides considerably low phase noise operation in Ku-band. This is due to the significant quality factor limits further degradation in phase noise. Interactive program was developed in Agilent's Advanced Design System (ADS) tool to choose better reflection coefficient considering trade-offs. 5.4 dBm output spectrum is achieved at 14.9GHz frequency without using buffer. VCO can be tuned in 14.85GHz to 14.95GHz frequency band using 0-22V varactor diode variable bias. Second order harmonic is-44 dBc below from the fundamental tone.

The noise figure of conventional TV varactor tuners is fairly high, when typical Si diodes, whose average resistance is 0.65Ω at 470 MHz, are used. Low noise tuners which comply with FCC noise requirements can be realized if low loss varactor diodes are developed. However, Si diodes with still lower losses can not be manufactured by conventional Si process technology with high production yield. Low noise Si rf transistors with a noise figure of 1.3 dB at 470 MHz is commercially available. However, noise figure improvement using these transistors at 470 MHz is only 1.0 ~ 1.2 dB when compared with conventional tuners. These low noise Si transistors are high in cost and low in production yield because the specification uniformities are insufficient.

This work presents the design of a high-bandwidth and high slew rate class-AB amplifier in a linear assisted hybrid converter for envelope tracking (ET) applications. ET has become prevalent for improving the efficiency of RF power amplifiers (PA) in portable devices when transmitting LTE signals. The class-AB amplifier in the hybrid converter provides the AC power to the PA, whereas the DC power is provided by a DC-DC converter. The class-AB amplifier is designed to track the LTE signal envelope, up to 20 MHz in bandwidth. Optimization is required to improve the efficiency of the system. A novel high-speed current-sense block is implemented to accurately sense the output stage currents of the class-AB amplifier. The amplifier is implemented in a 0.5–μ\Ά CMOS process, operates from a 3.6–5.0 V supply and is capable of driving a resistive load range from 20–4 Ω. The class-AB amplifier achieves 80 MHz UGF at a 4 Ω load, consuming roughly 33 mA quiescent current. Simulation results shows the tracking of 20 MHz LTE signals with an RMS error better than −34 dB.

With the overwhelming adoption of Orthogonal Frequency Division Multiplexing (OFDM) technique in many recent wireless communications standards, there have been extensive approaches to tackle the high Peak-to-Average Power Ratio (PAPR) problem that yields low efficiency in RF power amplifiers, which is the major drawback of OFDM systems. One of the approaches is to replace power amplifiers with the Linear Amplification using Nonlinear Components (LINC) block. However, this produces additional nonlinear distortions caused by amplitude or phase mismatch between two power amplifiers inside the LINC block. In this paper, we introduce a noble LINC calibration technique that utilizes the channel estimator block that is initiated by the Media Access Control (MAC) layer during the Distributed Interframe Space (DIFS) or Short Interframe Space (SIFS). For DIFS or SIFS, pilot symbols are allocated in a payload field and then the outputs of the transmitter are internally forwarded to the receiver to characterize the LINC channel with a pilot-aided Least Square Error (LSE) channel estimator. By applying a reverse distortion onto information symbols after the LINC channel distortion is obtained by channel estimation, we can significantly improve the Symbol Error Rate (SER) and Error Vector Magnitude (EVM) of the OFDM system with the LINC transmitter.