Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

Some non-ideal factors during circuit design of current steering digital to analog converter (DAC) are analyzed and summarized in this paper. A 12-bit classic current steering DAC has been analyzed and effects of these non-ideal factors has been validated. Meanwhile, non-idealities are also double checked in post-layout simulation. The whole circuit has been taped out in TSMC 0.25um BCD process, test and simulation results are compared at last. The comparison results show that the non-ideal analysis can be used to estimate non-linearity of current steering DAC and guide the circuit design of DACs.

Many satellite-based estimates use gauge information for bias correction. In general, bias-correction methods are focused on the intensity error and do not explicitly correct possible position or timing errors. However, position and timing errors in rainfall estimates can also lead to errors in the rainfall occurrence or the intensity. This is especially true for localized rainfall events such as the convective rainstorms occurring during the rainy season in sub-Saharan Africa. We investigated the use of warping to correct such errors. The goal was to gauge-adjust satellite-based estimates with respect to the position and the timing of the rain event, instead of its intensity. Warping is a field-deformation method that transforms an image into another one. We compared two methods, spatial warping focusing on the position errors and time warping for the timing errors. They were evaluated on two case studies: a synthetic rainfall event represented by an ellipse and a rain event in southern Ghana during the monsoon season. In both cases, the two warping methods reduced significantly the respective targeted (position or timing) errors. In the southern Ghana case, the average position error was decreased by about 45 km by the spatial warping and the average timing error was decreased from more than 1 h to 0.2 h by the time warping. Both warping methods also improved the continuous statistics on the intensity: the correlation went from 0.18 to at least 0.62 after warping in the southern Ghana case. The spatial warping seems more interesting because of its positive impact on both position and timing errors.

In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.

Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

A novel dynamic element match (DEM) named Segmented Thermo Data Weighted Average (STDWA) for the Nyquist-rate current-steering digital to analog converter (DAC) has been presented in this paper. In this method, when the input code changes, it only increase or decrease the chosen unit current source in order to reduce the signal glitch. Compared with full random DEM technique, this approach can reach a better static performance. Meanwhile, it can eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as well as other DEM implementations.

Conventionally, source followers have been used at the block of track-and-hold amplifiers (THA) for highspeed medium-bit analog-to-digital converters (ADCs). Even though the input signals of an ADC are fully differential, two single-ended source followers should be normally used. This is because differential source followers have some drawbacks. In this study, a wideband fully differential source follower is presented to obtain maximum efficiency of a fully differential THA. Because a cross coupling technique at the differential nodes is adopted, the performance of the proposed source follower is superior to the performance of conventional followers. The result of Spurious Free Dynamic Range(SFDR) is -66.92dBc for F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> /2 at F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> =500MHz. The SFDR of the proposed source follower is better by about 8.6dB than the SFDR of a conventional source follower under the same experimental conditions. To verify them, an 8-b cascaded folding ADC which includes the proposed source follower is fabricated with a 0.13um CMOS technology.

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

This letter presents a novel timing error detection and correction (EDaC) technique to reduce design margins in a near/sub-threshold RISCV-IM32 microprocessor. The proposed technique takes a snapshot of the datapath’s activity just before the launch of the next clock to determine if a timing error will occur. If so, it prevents the error at the last moment by gating the clock with one cycle. This avoids imposing additional hold constraints on the design and removes the need for a complex correction mechanism. The design is implemented in FDSOI 28 nm and achieves a margined minimum energy point (MEP) of 1.32 pJ/cycle at 3 MHz and 0.434 V. The EDaC technique robustly eliminates all voltage margin, resulting in an improved MEP of 0.92 pJ/cycle and 0.345 V at the same frequency.

A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 . It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.

This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μm×620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4–6 times, respectively.

This article presents a “three unary bits +five splitting bits + four binary bits” segmented 500-MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding method is between the unary decoding and binary decoding, in terms of number of switched elements. It can optimize the differential nonlinearity and output glitches of DAC, with a more simplified circuit scale than unary decoding method. Due to the data-transmission topology, both the proposed thermometer and splitting decoders feature lower transistor count and occupy less area than other competitors. Their low latency accommodates to fast synchronization control of current source switches and its beneficial to the spurious-free dynamic range (SFDR) improvement of DAC. When implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the 12-bit DAC occupies an active area of 536 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,340\,\,\mu \text{m}$ </tex-math></inline-formula> , with the proposed decoders occupying only 28 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,75\,\,\mu \text{m}$ </tex-math></inline-formula> . The DAC dissipates 17.20 mW at 500 MS/s with a 1.8-V analog supply and a 1.2-V digital supply. The differential and integral nonlinearities are measured to be 0.28 and 1.16 LSB, respectively. The DAC also features SFDRs of 68.83 and 62.06 dB for input signals of 6.34 and 239.74 MHz, respectively.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.