Statistical yield improvement under process variations of multi-valued memristor-based memories

The missing fourth passive essential circuit element-memristor enticed a big attention after HP labs evolved the first memristor device in 2008. Aside from the solid-state thin film memristor device, spintronic memristor was also feigned based on the magnetic technology. As it is at nano-scale geometry size, the memristor device suffers from the process variations in the fabrication process. Process variations swerve the actual electrical behavior of memristors from the desired values. This deviation results reduce the yield particularly in the memristor-based memory design. Therefore, it is serious to understand and distinguish the impact of process variations on memristor performance and yield and attempt to optimize the yield of the spintronic memristor-based memory arrays. In this paper, we describe a compact model of the spintronic memristor based on the magnetic-domain-wall motion mechanism.

This work evaluates the impact of process variations on the electrical behavior of a set of combinational cells considering different transistor sizing techniques: minimum sizing, logical effort and delay-optimized sizing. The optimization is done by a transistor sizing tool that employs geometric programming. The main point is to observe how transistor sizing techniques could be explored for the FinFET standard cells design. Results show that cells sized accordingly logical effort technique are more sensible to process variability when compared with minimum transistor sizing. The best process variability robustness is achieved by adopting the delay-optimized sizing technique.

More than forty years ago, Professor Chua predicted the existence of the memristor to complete the set of passive devices that previously includes only resistor, capacitor, and inductor. However, till 2008 the first physical realization of memristors was demonstrated by HP Lab. The unique properties of memristor create great opportunities in future system design. For instance, the memristor has demonstrated the similar function as synapse, which makes it promising in neuromorphic circuits design. However, as a nano-scale device, the process variation control in the manufacturing of memristors is very difficult. The impact of the process variations on a neural network system that relies on the continuous (analog) states of the memristor could be significant due to the deviation of the memristor state from the designed value. So a complete process variation analysis on memristor is necessary for the application in neural network. Due to the different physical mechanisms, TiO2-based memristor and spintronic memristor demonstrate very different electrical characteristics even when exposing the two types of devices to the same excitations and under the same process variation conditions. In this work, the impact of different geometry variations on the electrical properties of these two different types of memristors was evaluated by conducting the analytic modeling analysis and Monte-Carlo simulations. A simple algorithm, which is based on the latest characterization method of LER (line edge roughness) and thickness fluctuation problems, was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. We investigate the different responses of the static and memristive parameters of the two devices and analyze its implication to the electrical properties of the memristors. Furthermore, a process-variation aware device model can be built based on our work. Both corner model and statistical model can be provided depending on users’ requirements. Our device models make it possible for scientists and engineers to design neuromorphic circuits with memristive devices, and therefore, to convert virtual neural network in super computer to the real hardware memristive system in the future. Rather than the existing crossbar-based neuron network designs, we focus on memristor-based synapse and the corresponding training circuit to mimic the real biological system. The basic synapse design is presented, and the training sharing scheme and explore design implication on multi-synapse neuron system have been explored.

In this study, a novel method for the detection of recycled field-programmable gate arrays (FPGAs) is proposed. This method is based on with-in die (WID) process variation model over an exhaustive path characterization [referred to as exhaustive-fingerprint (X-FP)]. In the proposed method, X-FP is capable of fully characterizing frequencies on all paths in look-up tables (LUTs) using advanced ring oscillator (RO) design to exhaustively capture deterioration by aging. Although machine learning (ML)-based classification is often used for recycled FPGA detection, X-FP yields a large amount of measurement data, which cannot be appropriately handled by typical ML algorithms, if they are used as a feature vector. The proposed method utilizes the model parameters extracted by WID variation modeling as the feature vector in the ML algorithm. These model parameters simply and accurately represent the process variation for each FPGA. In this way, the ML-based fresh/recycled classification works very well with the simple feature vector. Experiments using 50 commercially available FPGAs reveal that X-FP can capture the degradation effects, which cannot be detected by conventional methods. Moreover, the WID modeling achieves 99.6% feature size reduction per one FPGA. It also demonstrates that the model parameters exhibit good distance properties between fresh and aged FPGAs. Additionally, the ML-based classification which uses a one-class support vector machine can successfully detect 2 aged FPGAs (48 h accelerated aging) without any misclassification and another 4 aged FPGAs (24 h accelerated aging) with a very few misclassifications as fresh FPGAs.

During fabrication process, mixed analog and digital integrated circuits (ICs) are more susceptible to process variations and physical defects than pure digital ICs. Therefore, it is beneficial to simulate the effects of process variations and defects on mixed-signal designs even before the design goes into production. Simulations of ICs having process variations are performed with Monte Carlo simulations. And, simulations of ICs having physical defects are called fault simulations. However, both simulation schemes require large numbers of instances. Consequently, simulation times can be extremely long, e.g. hours or days. In this System-on-a-Chip (SoC) era, mixed-signal designs are becoming more complex and thus impossible for traditional simulation schemes to be effectively applied. To dramatically reduce Monte Carlo simulation time and fault simulation time, a new behavioral simulation approach is proposed in this dissertation. Essentially, timing consuming detailed circuit simulations can be replaced by simple linear equations. A flash analog-to-digital converter (ADC) is used here to demonstrate the feasibility of proposed approach. The behavioral models for the flash ADC having process variations and physical defects are built. With these behavioral models, behavioral simulation programs are written in C++ to perform fast Monte Carlo simulations and fault simulations. For the small 3-bit flash ADC, the proposed method reduced the Monte Carlo simulation time, with 30 instances, from 180 hours to a mere 15 minutes. Such dramatic reduction in simulation time was achieved with a maximum prediction error of no more than 6%.

Over the last fifty years Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down, making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints. In this scenario, memristive devices have become promising candidates to replace or complement CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption as well as high scalability and density. Despite these advantages, the implementation of high-density memories based on memristive devices poses some challenges related manufacturing process variation and consequently, to their reliability during lifetime. This paper investigates the impact of manufacturing process variation on Resistive Random Access Memories (RRAMs). In more detail, an evaluation of the RRAM's functionality when considering different levels of manufacturing process variation is performed. The obtained results show that different parameters can degrade the functionality of the RRAM cell as well as that there is a relation between the performed operating sequence and the tolerated percentage of variability. Finally, it is important to mention that understanding how process variation impacts the functionality of RRAM cells is considered essential to guarantee their reliability during lifetime, also allowing to optimize manufacturing processes.

In sub-90 nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated parameters. Variations in the critical process parameters can result in significant fluctuations in the switching speed and leakage power consumption of different transistors in the same chip. In this paper, we study the impact of process variation on issue queues. Due to process variation, issue queues can take variable access latency. In order to work with nonuniform access latency issue queues, by exploiting ready operands of instructions at dispatch time, we propose a process variation aware issue queue design. Experimental results reveal that, for a 64-entry issue queue with half of the entries affected by process variation, our technique recovers most of the lost performance due to process variation and incurs a performance penalty of less than 2% with respect to the performance of issue queues without process variation.

Ultra-Deep Sub-Micron (UDSM) technology posts a serious challenge to the chip designer and EDA tools on the timing signoff accuracy. Timing signoff uncertainty due to in-die process variation, environmental variation, extraction accuracy and timing modeling accuracy become concerns for the timing signoff of UDSM SoC design. Traditional worst/best case timing sign-off methodology can cover the systematic process variation but can not model the in-die variation and environmental variation effects. On-chip-Variation timing analysis is now widely adopted to improve the design robustness under the consideration of timing signoff uncertainty. In this paper, we will present a case study of a 0.13 mm million gates SoC design on the various UDSM effects on timing signoff accuracy.

The bistable ring physical(ly) unclonable function (BR-PUF) is a novel electrical intrinsic PUF design for physical cryptography. FPGA prototyping has provided a proof-of-concept, showing that the BR-PUF could be a promising candidate for strong PUFs. However, due to the limitations (device resources, placement and routing) of FPGA prototyping, the effectiveness of a practical ASIC implementation of the BR-PUF could not be validated. This paper characterizes the BR-PUF further through transistor-level simulations. Based on process variation, mismatch, and noise models provided or suggested by industry, these simulations are able to provide predictions on the figures-of-merit of ASIC implementations of the BR-PUF. This paper also suggests a more secure way of using the BR-PUF based on its supply voltage sensitivity.

Today's analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits.

A mixed-signal circuit?s performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillator?s performance and device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross-correlation between oscillation frequency and device threshold voltage is obtained, and strong model-to-hardware correlation is observed through statistical analysis of simulation result and circuit measurement. The yield learning process of design, simulation, measurement, and statistical analysis is proposed.

Neuromorphic architectures are widely used in many applications for advanced data processing and often implement proprietary algorithms. However, in an adversarial scenario, such systems may face elaborate security attacks including learning attack. In this article, we prevent an attacker with physical access from learning the proprietary algorithm implemented by the neuromorphic hardware. For this purpose, we leverage the obsolescence effect in memristors to judiciously reduce the accuracy of outputs for any unauthorized user. For a legitimate user, we regulate the obsolescence effect, thereby maintaining the accuracy of outputs in a suitable range. We extensively examine the feasibility of our proposed method with four datasets. We experiment under different settings, such as activation functions and constraints such as process variations, and estimate the calibration overhead. The security versus cost and performance versus resistance range tradeoffs for different applications are also analyzed. We then prove that the defense is still valid even if the attacker has the prior knowledge of the defense mechanism. Overall, our methodology is compatible with mainstream classification applications, memristor devices, and security and performance constraints.

A novel fabrication process, based on selective wet etching and GaAs air-bridge was developed to produce AlAs/GaAs, AlAs/InAs/GaAs quantum dots double barrier quantum well sub-micron resonant tunneling diodes (RTD), and the peak to valley current ratio could be over 20. A new model of multilevel logic SRAM with RTDs was proposed.

Estimation of Number of Bits of Multi-valued Optical Memory by SNR Equalization and Extension to Two-layer Recording

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings