Studying dopant diffusion from Poly-Si passivating contacts

Studies of boron diffusivities on (001) and (110) substrate orientation in Si and Ge along vertical/out-of plane and lateral/in-plane directions study

Passivated, selective contacts in silicon solar cells consist of a double layer of highly doped polycrystalline silicon (poly Si) and thin interfacial silicon dioxide (SiO2). This design concept allows for the highest efficiencies. Here, we report on a selective laser activation process, resulting in highly doped p++-type poly Si on top of the SiO2. In this double-layer structure, the p++-poly Si layer serves as a layer for transporting the generated holes from the bulk to a metal contact and, therefore, needs to be highly conductive for holes. High boron-doping of the poly Si layers is one approach to establish the desired high conductivity. In a laser activation step, a laser pulse melts the poly Si layer, and subsequent rapid cooling of the Si melt enables electrically active boron concentrations exceeding the solid solubility limit. In addition to the high conductivity, the high active boron concentration in the poly Si layer allows maskless patterning of p++-poly Si/SiO2 layers by providing an etch stop layer in the Si etchant solution, which results in a locally structured p++-poly Si/SiO2 after the etching process. The challenge in the laser activation technique is not to destroy the thin SiO2, which necessitates fine tuning of the laser process. In order to find the optimal processing window, we test laser pulse energy densities (Hp) in a broad range of 0.7 J/cm2 ≤ Hp ≤ 5 J/cm2 on poly Si layers with two different thicknesses dpoly Si,1 = 155 nm and dpoly Si,2 = 264 nm. Finally, the processing window 2.8 J/cm2≤ Hp ≤ 4 J/cm2 leads to the highest sheet conductance (Gsh) without destroying the SiO2 for both poly Si layer thicknesses. For both tested poly Si layers, the majority of the symmetric lifetime samples processed using these Hp achieve a good passivation quality with a high implied open circuit voltage (iVOC) and a low saturation current density (J0). The best sample achieves iVOC = 722 mV and J0 = 6.7 fA/cm2 per side. This low surface recombination current density, together with the accompanying measurements of the doping profiles, suggests that the SiO2 is not damaged during the laser process. We also observe that the passivation quality is independent of the tested poly Si layer thicknesses. The findings of this study show that laser-activated p++-poly Si/SiO2 are not only suitable for integration into advanced passivated contact solar cells, but also offer the possibility of maskless patterning of these stacks, substantially simplifying such solar cell production.

Engineering aluminum oxide/polysilicon hole selective passivated contacts for high efficiency solar cells

This TCF project developed a thin-oxide (SiO₂)/polycrystalline silicon (poly-Si) passivated contact solar cell on CubicPV's (formally 1366 Technologies, Inc.) Direct Wafer® Product (DWP) kerfless wafers. The project used two NREL-developed technologies described in U.S. Patent No. 9,911,873, <em>Hydrogenation of Passivated Contacts</em> and U.S. Patent Application Serial No. 15/890,172, <em>Doped Passivated Contacts</em>. The project was motivated by a potential higher efficiency cell (compared to a PERC cell) using passivated contacts on the ultra-low cost kerfless wafers grown using the Direct Wafer process. The hope was to accelerate market adoption of the cell and wafer by delivering the lowest LCOE in the PV industry. The project tested both n-type and p-type SiO₂/poly-Si passivated contacts grown by thermal oxidation and plasma enhanced chemical vapor deposition (PECVD) of the poly-Si layer on DWP with varying wafer resistivities. Both deposition techniques are industry standards and thus economically viable methods for commercializing the contacts. The results indicated that both n-type and p-type poly-Si passivated contacts can be formed on polycrystalline DWP wafers, but implied open-circuit voltages (i_Voc) were limited to below 0.65 mV (compared with ~ 730 mV on n-Cz wafers). Diffusion of H to the Si/SiO₂/poly-Si interface was key to obtaining high i_Voc values. In this study, H was diffused from a high-temperature SiN_x layer deposited over the poly-Si layer during a high-temperature firing step, similar to one used for screen printed metals. The study concluded that poly-Si passivated contacts on DWP wafers passivated the surface of the wafers as well as PERC passivated surfaces, which use a less expensive dielectric layer stack. The project showed that Direct Wafer Product wafers grown by CubicPV could produce high i_Voc values (~0.647 mV), which could produce a cell over 20% efficient with proper processing and metallization. These cells, though not economically viable in 2024 as a stand-alone cell, could be integrated with a wide-bandgap top solar cell to form a two-junction tandem cell that could be viable under certain circumstances. This is because the bottom cell of a 30%, two-terminal tandem only needs to be a 20% cell under one-sun conditions. Thus, the DWP could be an ideal low-cost wafer for tandems. The project also revealed that a TOPCon type cell could be formed on a p-type DWP wafer using a P-diffused emitter and a p-type poly-Si contact. In fact, the p-type version of the poly-Si contact out-performed the n-type version for a variety of wafer resistivities, from highly doped to lowly doped. This curiosity requires more work to understand because on Cz wafers, the n-type poly-Si contact is of much higher quality than the p-type version.

In recent years, poly-Si based passivated contacts elevated the conversion efficiencies of crystalline Si solar cells to levels of 26%abs due to their outstanding electrical surface passivation performance and current transport characteristics. A major associated challenge, however, is the large parasitic light absorption within the doped poly-Si, regardless if the contacts are applied on the front and/or on the rear side of the solar cell. It, therefore, might be beneficial to confine the passivated contacts to local regions underneath the metal contacts. We present an effective and flexible laser-based approach to structure the poly-Si layer after its full-area deposition. Laser pulses with a pulse duration of 9 ps and a wavelength of 355 nm trigger an amorphization of the poly-Si surface. The minimum threshold fluence for amorphization is between 89 and 129 mJ/cm2. The a-Si layer, which is laterally homogeneous and up to (33 ± 4) nm in thickness, works as an etch barrier in an alkaline solution. The most robust barrier corresponding to the maximum thickness of the a-Si layer is found for a fluence of (270 ± 30) mJ/cm2. Besides the impact of the laser fluence on the etch resistiveness of the modified poly-Si layer, we study the role of oxygen during the laser process. We find that oxygen becomes incorporated into the material for certain laser fluences, which results in a more robust etch barrier. The amount of oxygen incorporated is below 3 wt. %. Eventually, we present a phenomenological model of our findings.

Of all the materials available to create carrier-selective passivating contacts for silicon solar cells, those based on thin films of doped silicon have permitted to achieve the highest levels of performance. The commonly used chemical vapour deposition methods use pyrophoric or toxic gases like silane, phosphine and diborane. In this letter, we propose a safer and simpler approach based on physical vapour deposition (PVD) of both the silicon and the dopant. An in-situ doped polycrystalline silicon film is formed, upon annealing, onto an ultrathin SiOx interlayer, thus providing selective conduction and surface passivation simultaneously. These properties are demonstrated here for the case of hole-selective passivating contacts, which present recombination current densities lower than 20 fA/cm2 and contact resistivities below 50 mΩ cm2. To further demonstrate the PVD approach, these contacts have been implemented in complete p-type silicon solar cells, together with a front phosphorus diffusion, achieving an open-circuit voltage of 701 mV and a conversion efficiency of 23.0%. These results show that PVD by sputtering is an attractive and reliable technology for fabricating high performance silicon solar cells.

This paper discusses how differently grown ultra-thin interfacial oxide of poly-Si based passivating contacts correspond to high-temperature annealing as well as its sensitivity to hydrogenation. It will be shown on symmetrical lifetime samples that tunnel oxide passivating contacts (TOPCon) featuring thermally grown interfacial oxide layer allow a higher optimum annealing temperature than those with thin wet-chemically grown oxides. These TOPCon structures can yield an excellent passivation quality with up to 741 mV iVoc and 88% iFF. Moreover, TOPCon samples annealed at low temperatures benefit more strongly from a subsequent hydrogenation process.

In this paper, we report our theoretical investigation on boron diffusion in silicon posterior to PAI (pre-amorphization implant) process in an effort to understand the physical mechanism for forming a shallow and abrupt junction. We performed numerical calculation for examining the characteristics of silicon atoms as a candidate for PAI species. Our KMC (Kinetic Monte Carlo) simulation revealed that PAI process helps to get a shallower junction than the case of PAI-free boron implantation and that Si-PAI process produces more amount of interstitial and vacancy which results in the reduction of so-called boron transient enhanced diffusion (TED). In addition, we made a comparison between Si-PAI and Ge-PAI in terms of the generation dynamics of defects and the effect on the subsequent diffusion of boron. Our KMC study on the interstitial distribution revealed that Si-PAI produces more interstitials than Ge-PAI whilst Ge-PAI help interstitials move further up toward the surface than Si-PAI during the subsequent annealing process.

Optimizing strategy of bifacial TOPCon solar cells with front-side local passivation contact realized by numerical simulation

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p/sup +/-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF/sub 2//sup +/-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF/sub 2//sup +/ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 /spl Aring/, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm/sup 2/ at -5 V were obtained. As the junction depth shrank to 300 /spl Aring/, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm/sup 2/, respectively. These results demonstrated that a uniform ultrashallow p/sup +/-n junction can be obtained by using a thin Si-B layer as a diffusion source.

An aluminum oxide (AlOx)/silicon nitride (SiNy) dielectric stack was developed using an industrial plasma‐enhanced chemical vapor deposition (PECVD) system with low‐frequency (LF) plasma source for the surface passivation of undiffused textured p‐type crystalline silicon. The median recombination current density is 4.3 fA cm−2 as determined from photoconductance decay lifetime measurements and numerical device modeling. To the best of our knowledge, this is the first time to present a high‐quality LF‐PECVD AlOx/SiNy passivation stack on undiffused textured p‐type crystalline silicon wafers, which are cleaned with industrial processes using HF, HCl, and O3. The simulation agrees well with the measured effective carrier lifetime if the velocity parameters of 5.6 cm s−1 for holes and 803 cm s−1 for electrons are applied with a fixed negative charge density of −3 × 1012 cm−2. The process integration of developed AlOx/SiNy dielectric stack is successfully demonstrated by fabricating p‐type back junction solar cells featuring a poly‐Si‐based passivating contact at the cell rear side. As the best cell efficiency, we achieve 24.2% with an open‐circuit voltage of 725 mV on a M2‐sized Ga‐doped p‐type Czochralski‐grown Si wafer as independently confirmed by ISFH CalTeC.

Aggressive scaling of complementary metal–oxide–semiconductor (CMOS) devices requires gate dielectrics with an oxide equivalent thickness, tox,eq∼1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance limitation in field-effect transistors (FETs) with homogeneous oxide gate dielectrics &amp;lt;1.7 nm. Boron diffusion from p+ poly-Si gate electrodes in p-channel FETs leads to additional electrical problems for oxide thicknesses &amp;lt;3 nm. Interfacial nitridation improves reliability in n-channel FETs; however, by itself, it is not effective in p-type metal–oxide–semiconductor FETs due to boron pileup at the Si–dielectric interface. Proposed solutions include top-oxide surface nitridation and the integration of composite oxide–nitride dielectrics into CMOS devices. This review discusses the integration of hydrogenated silicon nitride films, prepared by remote plasma-enhanced chemical-vapor deposition, into electrical devices with composite oxide–nitride (ON) gate dielectrics. FET devices with ON dielectrics having the same oxide-equivalent thickness, tox-eq and gate dielectric capacitance as devices with homogeneous oxide gate dielectrics display improved performance and reliability. However, reductions in direct tunneling current due to increased physical thickness are below expectations based on tunneling calculations which assume the tunneling mass of electrons in nitride films is approximately the same as in SiO2. The combination of a lower electron tunneling mass and a reduced conduction-band offset energy (i) places important limitations on the extent to which devices with ON gate dielectrics can meet the aggressive scaling needed in advanced CMOS devices, and (ii) raises important questions that have to be addressed when evaluating alternative high-K dielectrics such as Ta2O5, TiO2, and Al2O3. However, tunneling can be reduced by combining monolayer interface nitridation with ON stacks.

Highly passivating, hole selective contacts are required for future high efficiency silicon solar cells. This work investigates selected dielectrics as potential SiOx replacements to act as hole selective contacts. AlOx and SiNx were identified as good candidates due to their low valence band offsets to silicon and proven surface passivation capabilities. Simulated J-V curves show AlOx and SiNx maintain acceptable contact resistivities at thicknesses below 1.4 and 1.7 nm, respectively. The SiOx hole contact was found to become extremely resistive even at thicknesses <1 nm, suggesting that either pinholes dominate conduction, or the band offset parameters differ from those in real TOPCon structures. The passivation of the dielectrics was also simulated, with SiOx outperforming both AlOx and SiNx primarily due to the excellent interface. Additionally, the effect of nanolayer built in charge was investigated. Charges below 1012 q/cm2 were found to have little effect, while negative charges above 1012 q/cm2 resulted in reductions in the contact resistivity and recombination current. The calculated selectivity for a 1.4 nm layer of AlOx was 12.9, while a value of 13.8 was calculated for SiNx at typical intrinsic charge levels.

Control of dopant diffusion during high-temperature cycling is critical in forming shallow electrical junctions in silicon as needed in integrated-circuit manufacturing. However, junctions formed by implantation can be anomalously deep due to a transiency associated with ion-induced defects which greatly enhances dopant diffusion. The purpose of this work was to investigate methods of defect engineering the implantation process to control or eliminate transient-enhanced diffusion (TED). TED of boron has been attributed to excess interstitials introduced into the lattice during implantation, known as the plus-one model. Effects of pre-amorphization (i.e., amorphization prior to dopant implantation using isoelectric ions) on TED of boron, and particularly, the role of the end-of-range (EOR) defects at the amorphous-crystalline interface, are discussed. These EOR defects were varied by altering the implantation conditions during pre-amorphization. Also, other means of controlling the transiency are discussed, in particular, the use of high-energy ions to introduce excess vacancies into the lattice where dopant diffusion occurs. These vacancies are shown to interact with the excess interstitials introduced during dopant implantation to suppress TED.

Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5nm conformal shallow junctions at low energy with no silicon structure damage. N-type PH3 plasma assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma assisted doping at high wafer temperature showed no structure damage even at a high incident energy condition with a bias power applied to the wafer, while a shallow junction of less than 7nm of Xj formation was achieved with low incident energy condition without bias power. Adding a silicon surface modification step when using the decoupled plasma condition prior to PH3 doping was found to enhance the dopant level and lower Rs dramatically. Various annealing techniques were compared to understand the impact to dopant activation and levels to form shallow junctions of less than 7nm.