Superconducting Through-Silicon Coplanar Waveguide Interconnects for High-Bandwidth Three-Dimensional Integration

This paper describes fabrication, characterization and simulation of low-loss coplanar waveguide (CPW) interconnects on low-resistivity silicon substrate. The fabrication of CPWs is low-temperature (below 250/spl deg/C) and incorporates a spin-on low-k dielectric benzocyclobutene (BCB) and self-aligned electroplating of copper. The performance of CPWs is evaluated by high-frequency characterization and EM simulation. CPWs with different line width (W) and line spacing (S) are investigated and compared. Using a BCB layer as thick as 20 /spl mu/m, CPW fabricated on a low-resistivity silicon substrate exhibits an insertion loss of 3 dB/cm at 30 GHz.

Transmission line parameters such as characteristic impedance Z0, effective dielectric constant eeff, attenuation constant α of suspended microstrip line on multilayer low resistively silicon substrate are investigated using full wave FEM simulator HFSS. Effect of variation in the thickness of Si3N4, polyimide and metal layers on attenuation are studied. Due to suspended nature, significant reduction in transmission loss is observed in the simulation at 60 GHz frequency. Discontinuities such as open end, gap and step in width of strip conductor are analyzed to extract their lumped equivalent circuits which can be used in the design of integrated circuits.

This thesis presents a specialization of the integral equation (IE) method for the analysis of three-dimensional metallic and dielectric structures embedded in laterally unbounded (open) layered media. The method remains basically spatial but makes use of extensive analytical treatment of the vertical dependence of the problem in the 2D Fourier-transformed domain. The analytical treatment restricts somewhat the class of structures that can be analyzed. Still, the field of applicability remains very large, and includes most printed circuit and integrated circuit structures. The method is developed in full numerical detail, from first principles down to the properties of new Green's functions and the computation of particular types of convolution integrals. We show how the memory and time complexity are considerably reduced when compared to the requirements of the analysis of general 3D structures. With the newly developed tool, it is possible to deal with some peculiar characteristics of microwave and millimeter-wave circuits and antennas. Most noteworthy among these is the presence of thick metallizations (either electrically, or relative to circuit features). A novel full-wave analysis of arbitrarily shaped apertures in thick metallic screens is presented. This is compared to other methods, both full-wave and approximate, and demonstrated to offer excellent accuracy. Comparison with measured data, obtained from specially constructed prototypes, further validates the new technique. A second application is to the analysis of airbridges in coplanar waveguide (CPW) and slotline (SL) circuits. Comparison of measured and simulated data validates again our technique and provides valuable information about the behavior of CPW-fed slot loop antennas. Among the more specific applications, particular attention is devoted to the analysis and design of submillimeter-wave integrated dielectric lens feeds. These were object of study in the frame of a European Space Agency project, Integrated Front-End Receivers (IFER), which our Laboratory carried out in cooperation with a team at University of Toronto. The analysis method developed in this work encompasses and extends all previous work done at our Laboratory (LEMA) related with the analysis of this kind of feed. Together with the advanced 3D ray-tracing code developed at University of Toronto, it is possible to gain a high degree of insight into the behavior of these integrated receivers.

An analysis of new broadside-coupled coplanar waveguides (CPW) having a completely asymmetrical structure, suitable for hybrid and monolithic microwave and millimeter-wave integrated circuits requiring broad bandwidths as well as loose and tight couplings, is presented. The results of the investigation, performed based on the spectral-domain analysis, demonstrate the versatility of the asymmetrical broadside-coupled CPW as compared to its symmetrical counterpart.

Three-dimensional integration is a pivotal strategy for advancing the integrated circuit performance beyond traditional scaling limits. Herein, we report a monolithic 3D (M3D) integration technology using carbon nanotube (CNT) networks to fabricate four-layer complementary metal oxide semiconductor (CMOS) thin-film transistors (TFTs), representing the highest layer count to date for CNT-based CMOS M3D devices. The vertically stacked structure achieves enhanced integration density through layer-by-layer stacking with interlayer isolation via low-temperature-processed dielectrics, enabling the stable operation of N-type and P-type CNT-TFTs in separate layers. Functional IC units, including CMOS inverters and trans-impedance amplifiers (TIAs), were successfully implemented using this four-layer architecture. Furthermore, vertical integration of the M3D TIA with a molybdenum disulfide (MoS2) photodetector realized a monolithic optoelectronic sensing system, achieving primary amplification of photocurrents with a trans-impedance gain of 7.21 × 103 Ω. This work validates the feasibility of CNT-based M3D integration for high-density, multifunctional ICs and paves the way for next-generation optoelectronic systems and power devices.

This paper introduces and studies the design of a multimode ultra-wideband filter based on a coplanar waveguide (CPW) transmission line. The filter is composed of a multimode resonator consisting of two high and low impedance lines. Through the coupling between the input and output ports of the CPW transmission line and the multimode resonator, an ultra-wideband dual-mode filter is obtained. There are 2 transmission poles in the filter and it has a center frequency of 6.8 GHz, a bandwidth coverage of 3.1−10.5 GHz, and a relative bandwidth of 110%. The designed filter has the advantages of simple structure, compact size, easy integration, and good performance in CPW circuits.

A finite-element simulation has been implemented to evaluate the slow-wave-mode propagation characteristics in metal-insulator-semiconductor (MIS) waveguiding structures. Particular emphasis has been placed on coplanar waveguides compatible with silicon integrated circuits (ICs), with an objective of evaluating the effect of inhomogeneous doping on propagation characteristics. The simulator has been successfully benchmarked against a number of cases presented in the literature, including MIS coplanar waveguides. The effect of inhomogeneous doping and finite metallization in maintaining a large slowing factor while reducing the attenuation constant and increasing transmission-line Q is presented, and constraints on slow-wave-mode passive components are discussed.

We present the design and development of an ultra-violet (UV) LIGA (a German acronym for electroplating, lithography and molding) micromachining process on silicon substrates at microwave/millimeter wave frequencies. The process employs an ultra-thick negative photoresist SU-8 that can be spin-coated and processed using conventional lithography techniques. Using this process, we have developed micromachined coplanar waveguide (CPW) interconnects on Si substrates. The conductor-backed micromachined CPW on Si (7.2 /spl Omega/-cm) achieves a measured attenuation of 0.18 dB/cm at 20 GHz.

It is now widely recognized that three-dimensional (3D) system integration is a key enabling technology to achieve the processing speeds and performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D stacked ICs, interlayer microfluidic cooling scheme is adopted and analyzed in this study. The effects of cooling scheme and essential geometry variations on the routing completion and congestion of electrical interconnect are quantitatively analyzed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that refrigerants in two-phase flow are thermally preferred due to the higher heat transfer coefficients, and relatively constant fluid temperature throughout the microchannel. However, the large internal pressure and pressure drop act as significant limiting factors in realizing the merits of two-phase cooling. It is also concluded that integration of high performance hot-spot thermal management is a key to addressing a challenge of mass flow rate mal-distribution.

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

A broadband vertical transition from coplanar waveguide (CPW)-to-microstrip modes is presented. The transition has a double resonance and can be tuned for very wide-band operation. The CPW-to-microstrip modes coupling technique is useful for the vertical integration of multi-layer millimeter-wave circuits, packaging and antenna feeding networks. A vertical transition has been fabricated on 100 mum silicon substrate for operation at W-band frequencies and shows less than 0.3 dB of insertion loss and better than 12 dB of return loss from 75 to 110 GHz. A 94 GHz CPW-fed microstrip antenna showing a 10-dB bandwidth of about 30 % has been built using the same transition technique.

Microwave and millimeter-wave integrated circuits and distribution networks often require two transmission lines to cross over each other. In this paper, experimental measurements and 3D-Finite Difference Time Domain (FDTD) analysis are used to characterize Coplanar Waveguide (CPW) and Finite Ground Coplanar (FGC) waveguide crossover junctions for the first time. It is shown that FGC crossover junctions have approximately 15 dB lower coupling than CPW crossover junctions with no degradation in return and insertion loss.

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

3D IC technology with transistors stacked on top of one another in multiple silicon layers has long been a vision for future technology directions to provide a breakthrough towards higher circuit density and functionality. While the idea is simple, techniques to obtain high performance multi-layer transistors are extraordinarily difficult, and it is only recently that such technology has become feasible. In this paper, various techniques to form 3D circuits are reviewed. Recent development of a promising technology to achieve three-dimensional integration using metal-induced-lateral-crystallization is described. Preliminary results for 3D inverters and ring-oscillators have demonstrated the viability of 3D integrated circuits. Finally, the challenges for realization of 3D circuits are discussed.

In this paper, we design and fabricate a radio frequency (RF) signal transmission structure for a 3D stacked structure. Usually, this structure uses co-planar waveguide (CPW) and Through Silicon Via (TSV) to realize the horizontal and vertical RF signal transmission on the same interposer respectively. With the help of micro-bump, we can transport RF signal in a stacked structure. Furtherly, we design and fabricate a patch antenna with a stacked structure, fed by the structure we proposed. Through the measurement of the antenna, we determine the effectiveness of this transmission structure.