Switched-Capacitor-Based Three-Phase Five-Level Inverter Topology With Reduced Components

The modified five-level multilevel inverter ensures better conversion of power in multiple voltage steps to achieve improved power quality, lower switching losses and higher voltage boost capability. For comparison purposes, existing H-bridge multilevel inverter topology are analyzed under various switching schemes and new updated five-level multilevel inverter topology have been created. This five-level multilevel inverter has been applied with a solar PV device, initially the maximum power produced from a solar PV panel is derived by a regulated duty cycle using a perturbation and observation (p and o) algorithm. Controlled switching pulses are applied to five MLI speeds to transform DC to AC. The five-level multilevel inverter switching series along with the operating parameters of the solar PV panel is briefly described in this article. The five-level MLI program model for the solar PV network was developed and the PSCPWM (phase-shifted carrier pulse width modulation) was implemented based on a 6 KHz switching frequency. The MATLAB software is used to simulate the results.

Multilevel inverter is a converter that converts DC power sources into AC power sources with the voltage output higher than two levels. Conventional multilevel inverter topology for five levels that is currently developing generally uses eight components of power switches. In this paper, a five-level multilevel inverter topology is proposed by reducing the power switch component to four and aided with two pin diodes and capacitors as voltage couplings. The simulation with MATLAB that has been done shows various advantages of this topology compared to conventional multilevel inverter topologies. Results and discussion This topology compare the switching techniques used between Pulse Width Modulation (PWM) and Sinus Pulse Width Modulation (SPWM) for five-level multilevel inverter. Cohesiveness in switching techniques topology is proposed and validated by using passive filter. The harmonic analysis performed by the proposed topology could reduce the output voltage with the low harmonics.

This article proposes two generalized multilevel inverter configurations that reduce the number of switching devices, isolated DC sources, and total standing voltage on power switches, making them suitable for renewable energy sources. The main topology is a multilevel inverter that handles two isolated DC sources by ten power switches to create twenty-five voltage levels. Based on the proposed main topology two generalized multilevel inverters are introduced to indicate flexibility in designing and also to minimize the number of elements. The optimal topologies for both extensive multilevel inverters are derived from different design objectives such as minimizing the number of elements (gate drivers, DC sources), achieving a large number of levels, and minimizing the total standing voltage. The main advantages of proposed topologies are a reduced number of elements than other multilevel inverters based on the comparison studies which is performed among the proposed topologies and other topologies. The power loss analysis and standalone PV application of the proposed topologies are discussed. The experimental results are presented for the proposed topology to demonstrate the correct operation of the proposal.

The series connection of low-power modules is an alternative solution to realize a multilevel inverter. Unlike a cascade connection, the series connection approach significantly reduces the number of isolated dc sources, thereby the design complexity, cabling of the transformer, and overall system cost become low. In this article, the operation of the series-connected multilevel inverter is presented for a five-level operation, and it is realized by using two three-level half-bridge diode clamp converter modules per phase. Hence, each phase of the series-connected multilevel inverter requires a single isolated dc source. In the series-connected multilevel inverter, the net dc-bus voltage will be equally distributed between four dc-bus capacitors. Therefore, the converter generates a multilevel voltage waveform with uniform steps and ensures equal voltage stress on the semiconductor devices. To achieve these objectives, a space vector pulsewidth modulation scheme with an additional voltage balancing approach is employed. The feasibility of series-connected multilevel inverter is validated through simulations and a scaled-down laboratory prototype under steady-state and transient conditions.

Multilevel inverters (MLIs) are becoming commonly increasing in high- and medium-power applications. This is because MLI has various intrinsic advantages over conventional two-level inverters, including reduced device ratings, high-quality output, and so on. Most of the traditional topologies are still used in key applications, and there is an increased attentiveness to emerging multilevel topologies to minimize the number of gate drivers, power semiconductor devices, and/or isolated DC sources. Although MLIs have a promising future in industry-oriented applications, their commercial acceptance has been constrained by their size cost, excessive device count, and switch complexity. To convey the drawbacks of MLIs, academics are continually developing next-generation topologies known as reduced switch count (RSC) MLIs. For various reasons throughout the past 10 years, many MLIs with RSC topologies have been described. In this study, an overview of some of the more newly proposed multilevel inverter network topologies that achieve the legitimate goal is presented.

In the present paper, single phase multilevel inverter using switched capacitor units is proposed. The switched capacitor unit (SCU) is used in the multilevel inverter will increase the dc supply voltage at the input without using transformer by operating the capacitors in parallel and in series. The SCU comprises one dc source, two semiconductor switches, power diode, and capacitor. The proposed topology does not require the charge balancing operations, which results reducing the cost of the overall circuit. In addition to that, it does not required H-bride module to alter the polarity of the output voltage, which will lead to minimum required semiconductor power switches. The proposed topology is compared with the conventional similar architectures in terms of power semiconductor switches, power diodes, dc power supplies. Finally, to confirm the proposed architecture performance, simulation results are presented.

This paper proposes a grid-connected Photovoltaic (PV) system based on a multilevel Current Source Inverter (CSI) topology. The topology proposed here consists of parallel-connected CSI modules operating at a very low switching frequency. For n number of inverter modules, 2n+1 current levels are resulted in the output. In the multilevel inverter topology, each inverter module has its own PV source, Maximum Power Point Tracking (MPPT) unit, and DC-link current controller. Unlike earlier proposed multilevel CSI topologies, the proposed topology has a single AC-side current controllers, lowering the requirements for AC-side sensors and filters. To demonstrate the performance of the multilevel inverter based on CSI, two inverter units are considered in this study. The simulation studies are carried out in PSCAD/EMTDC environment.

A multilevel PWM voltage source inverter, especially a five-level one, is introduced to obtain a static var compensator (SVC) as a large scale power source. The multilevel inverter has many advantages, such as better utilization of the switching devices, lower switching frequency at each semiconductor switch and reduced harmonics. In this paper, the SVC with five-level inverter is modelled using circuit DQ transformation and completely analysed including DC and AC characteristics. It is also pointed out that the modulation indexes depend on the values of the DC side capacitors to meet the DC side voltage balancing, Finally, through the experimental results from a 5kVA SVC, the validity of the analyses and the feasibility of the var compensation system are shown for high power applications.

An isolated four channel dc/dc converter with zero voltage switching is proposed as the front-end of multiple inverter structures to integrate renewable and other low voltage energy sources to micro grids. The interleaving technique is adopted to connect each module of proposed converter to a common dc source. This dc source can be a fuel cell stack, PV panels, battery, or any other low voltage dc source. All four channels are interleaved and a phase shift of 90° is provided between the gate signals of each channels, which reduces the input current ripple. The output port of the proposed converter provide four isolated and regulated dc voltages. These isolated dc sources can be connected in series or parallel or series-parallel manner to obtain required dc-link voltage of various inverter structure. Issues like capacitor voltage balancing of diode clamped multilevel inverters can overcome through the proposed converter. By incorporating a coupled inductor for isolation and energy storage along with voltage multiplier circuit, the proposed converter can achieve higher voltage step up with lower turns ratio and lower voltage stress at moderate duty ratio. Hence, mosfets of low voltage rating (low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> (ON)) can be utilized to reduce conduction loss. A 2 kW prototype of the proposed interleaved dc/dc converter is developed and tested with diode clamped three-level inverter, five-level inverter, and three-phase two-level inverter to verify the design.

Three-phase multilevel inverter for grid-connected distributed photovoltaic systems based in three three-phase two-level inverters

A new seven-level multilevel inverter (MLI) with dual isolated input for grid-connected photovoltaic energy transfer system (PETS) is proposed in this paper. It has six unidirectional and one bidirectional semiconductor switches for realizing the seven-level output. The MLI finds application in photovoltaic (PV) energy transfer systems, where the requirement of two isolated DC sources is fulfilled by proper solar panel management. The bidirectional switch reduces the control overburden and improves circuit compactness as compared with the cascaded H-bridge MLI. The grid-connected PETS is designed to deliver the available PV power to load, connected in the distribution bus, as well as injects the remaining active power to the grid with a unity power factor (UPF). Moreover, PETS mitigates the reactive and harmonic demand of load irrespective of PV output and maintains the grid power quality within the IEEE-519 standard. The steady-state and dynamic performance of the proposed system is validated by using MATLAB/Simulink model, and the prototype for the MLI is developed and tested in the laboratory.

In this paper a novel topology of switched capacitor based multilevel inverters is proposed. In this topology, to increase the output voltage levels and to add the voltage boosting capability, several switched capacitor units are cascaded in series. Having voltage boosting capability and generating maximum number of output voltage levels using minimum number of circuit components, is a merit for this topology. To highlight the attributes of the proposed topology, it is compared with other recently proposed multilevel inverters on number of circuit components such as power electronic switches, diodes and capacitors, voltage boosting capability, total standing voltage, cost and efficiency. The comparison results verify the superiority of the proposed topology over other proposed topologies on number of circuit components, and number of output voltage levels. It is also clear that, this topology has lower voltage stress on power electronic switches, which makes it an appropriate solution for industrial applications. Finally, to show the capabilities of the proposed topology, and to verify the accurate operation of the topology, circuit analysis as well as the experimental results are provided.

Voltage fluctuation is one of the major issues encountered in multilevel inverters as it requires many isolated DC sources. The effect of source voltage unbalance results in unbalanced load current with reduced modulation index. This paper proposes slope suppression techniques to compensate for the source unbalance and achieve balanced output current. It is operated at its maximum modulation index. In order to analyze these effects, two methods namely carrier slope suppression (CSS) and reference slope suppression (RSS) techniques have been identified. An even level multilevel inverter topology comprising of a base six switch inverter, cascaded with H bridge modules in each phase is considered for analysis. Conventional sinusoidal pulse width modulation (SPWM) is developed for a four level inverter and its inadequacy to produce a balanced output under unbalanced voltage condition is analyzed. A comparison is made among the SPWM, CSS and RSS techniques. To validate the algorithm, simulation and experimental verification was done using MATLAB/SIMULINK and NEXYS 2 SPARTAN 3E FPGA with 3ϕ Induction Motor load.

Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.

Conventional multilevel inverters (MLI) incorporate many independent dc sources and switches, which adds to the overall system's cost and complexity. This article presents a detailed analysis of a reduced switch single‐phase five‐level inverter for medium‐ and high‐power applications. The comparison of the proposed topology with traditional and recently developed MLI topologies shows that the topology proposed has a smaller number of circuit elements, isolated dc sources, and voltage stress of half of the supply voltage on 50% of switches. Reducing the number of components and sources reduces the complexity and total cost of the inverter. These reduced switches voltage stresses increase the overall system reliability. The MATLAB/SIMULINK simulations for different load changes were carried out for analysis in software mode. The scaled‐down prototype is used for the validation of simulation analysis. The components comparison was also carried out to list the advantages of this topology over other MLI configurations.