Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study

As design features increase and sizes shrink and more transistors are squeezed into a system-on-a-chip (SoC) IC, the sheer number of on-chip devices far outstrips a design team's ability to harness the full benefits of all the transistors. Furthermore, according to a Synopsys survey, one of the main reasons for bugs in first silicon designs is logic bugs. To address those needs the EDA community provides a large set of tools for the logic designer that includes simulation, formal verification and linting among others. To fully benefit from these tools, the logic design teams should use them as one environment rather than as separate tools. In this paper, we will demonstrate how this usage of linting, simulation and formal verification as one environment can provide a solution that is greater than the sum of its parts. Several groups at Intel from the Digital Enterprise Group (DEG) and the Mobility Group (MG) are reporting good results by using this flow.

Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).

Online testing is a process of functional verification of microprocessors produced in silicon or their FPGA-prototypes, i.e. post-silicon verification. This type of testing differs both from the manufacturing testing, aimed at checking the workability of manufactured chips (e.g., absence of physical defects, admissibility of physical characteristics) and from simulation-based pre-silicon functional verification of microprocessors models (where internal microprocessor signals are available for observing, and the execution process can be controlled). Post-silicon verification enables to rapidly run huge numbers of tests and detect bugs missed during pre-silicon functional verification. Tests for microprocessors are usually represented by executable programs. Accordingly, the main tasks of online testing are high-performance generation of test programs in the given ISA and creation of a test environment responsible for launching programs, assessing the correctness of their execution by a microprocessor, diagnosing errors, and interacting with the outside world. This paper examines the problems arising in the development of online testing systems (online test program generators), reviews existing solutions in this area, and, on the base on them, proposes a promising approach to organizing online testing.

Host-guest interactions of coumarin-based 1,2-pyrazole using analytical and computational methods: Paper strip-based detection, live cell imaging, logic gates and keypad lock applications

The PCIe 6.0 specification introduces the L0p low-power substrate, enabling dynamic link width scaling to reduce power consumption without interrupting data flow. This feature presents unique verification challenges due to its complex handshake mechanism, precise timing requirements, and backward compatibility needs. Pre-silicon verification using formal methods and simulation is essential to validate L0p logic before silicon fabrication. Formal verification confirms the correctness of state transitions, entry/exit conditions, and deadlock freedom, while simulation examines lane activation/deactivation sequences and data integrity during width changes. This article details the verification methodology for L0p, including formal proofs of the handshake process and extensive simulation of lane scaling events. Case studies highlight subtle design bugs uncovered and resolved in pre-silicon, including simultaneous width-change request deadlocks and lane reactivation sequence errors, avoiding costly post-silicon debugging. Comprehensive pre-silicon validation ensures PCIe 6.0 devices can safely leverage this power-saving mechanism while maintaining performance and interoperability.

Advancements in manufacturing technologies allow to integrate an ever increasing amount of functionality into single System on Chip devices (SoCs). This not only causes the well-known productivity gap, it also challenges the proper verification of these designs. While the efficiency of pre-silicon verification of purely digital designs is continuously increased, either by the use of sophisticated Hardware Verification Languages (HVLs) or with powerful software suites, there is a lack of applicable concepts for mixed-signal designs. Furthermore, pre- and post-silicon verification activities are still often treated separately preventing to exploit possible synergies. For these reasons there is a great need for new innovative mixed-signal verification methods and flows that are able to cope with a soaring amount of functionality further aggravated by a shrinking time-to-market. This paper presents an approach to use abstract test descriptions written in Perl (1) to increase the efficiency of the verification process of complex mixed-signal SoCs designs in a SystemC simulation environment and (2) to enable information exchange between pre- and post-silicon activities. Since Perl and SystemC are distinct languages several approaches to link them together were elaborated and are presented in this paper. Their suitability with respect to several key aspects is compared and their effectiveness for pre-silicon verification is evaluated on the basis of an example test case.

Silicon validation - proving a chip works correctly at speed and in system under different operating conditions - is always necessary, even for a "perfect" design. Silicon debug - finding the root cause of a malfunction - is necessary whenever a design is not flawless. First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. The difficulty of silicon validation will increase at 65 nm and below because existing ad hoc methodologies don't scale with the unprecedented levels of SoC device complexity. Even the most sophisticated SoC design methodology cannot fully account for all the parameters that affect silicon behavior, or for all logic corner cases occurring in the life of a chip working at speed and in system. For example, the simultaneous occurrence of two unlikely events might not be anticipated pre- silicon, so it is never simulated or analyzed; however, when it occurs in system, it can cause unexpected behavior. Presilicon verification methods - simulation, emulation, FPGA prototyping, timing analysis, and formal verification - don't address many deep-submicron problems that occur in the actual device.

Formal property verification exhaustively verifies logic designs against some desired properties of the designs with respect to all possible input sequences of any length. Without abstraction, state-of-the-art formal proof engines usually cannot verify properties of designs with more than a couple of hundred registers. As a result, formal property verification relies on automatic abstraction techniques to verify real-world logic designs.Abstraction refinement, first introduced by Kurshan in the tool COSPAN, is one of the most practical automatic abstraction methods. Abstraction refinement incrementally refines an abstract model of the design by including more and more detail from the original design until the underlying formal property verification engine verifies or falsifies the property.In this talk we give an overview to some of the most interesting abstraction refinement techniques that have enabled the formal verification of VLSI logic designs with millions of logic gates.

Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address the validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the hybrid quick error detection ( H -QED) approach that overcomes validation and debug challenges for hardware accelerators by leveraging HLS techniques in both the presilicon and post-silicon stages. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it is detected) by 2–5 orders of magnitude with one cycle latencies in presilicon scenarios and bug coverage threefold higher compared to traditional validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs an 8% accelerator area overhead with negligible silicon performance impact for post-silicon stage, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.

Building simulation models are typically not used to generate the documentation required for bidding and project delivery of commercial building systems, or for their semantic modeling and commissioning. This paper presents a software tool that aids in digitizing the control delivery process, spanning simulation during design to implementation and formal verification during commissioning. The tool can generate from Modelica models digital documentation of control sequences. This digital documentation, along with other project drawings and specifications can be used for project bidding. It can also be used for implementation of control sequences through machineto-machine translation to commercial legacy control products, for which we are currently developing the proposed ASHRAE Standard 231P based on the presented work. Moreover, as-installed control sequences can be formally verified against the design specification, and a semantic model in Brick can be exported to aid in configuration of building analytics and fault detection. The paper presents what we believe is the first translation of a Modelica-implemented control sequence to a native implementation on a commercial control platform, using the webCTRL product line from Automated Logic. The paper also shows how a webCTRL implementation can be formally verified against its Modelica specification. These use cases have all been demonstrated with a prototype implementation that is now being further developed.

Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing.

As real-time applications become increasingly demanding, complex CPU architectural techniques like Instruction Level Parallelism (ILP) and Very Long Instruction Word (VLIW) are the new norm. Processors have evolved along a similar trajectory to include twice the number of instructions compared to its predecessor, the ability to fetch a larger instruction packet and execute multiple instructions simultaneously. To ensure that the design meets the specification it's imperative to verify every possible operand combination as well as sequencing of instructions. This demands deployment of novel techniques which can reduce verification effort without compromising on the quality. In this paper, we propose a Formal Verification (FV) based “divide-and-conquer” approach to CPU verification which utilizes executable specification. We propose dividing the verification effort into two levels of design abstraction, namely basic functional unit level (e.g. Adder (ADD), Multiply and Accumulate (MAC), etc.) and module level (e.g. collection of functional units like ALU). FV allows us to cover the vast state space while avoiding the burden of developing corresponding stimulus. By automating the verification flow from an executable specification, we eliminate the possibility of human error and standardize the setup across functional units. We leverage these techniques to accomplish comprehensive verification goals and achieve design sign-off. When implemented, we were able to achieve 50% reduction in the CPU verification effort and identify corner case bugs that would have been impossible to find using Dynamic Verification.

This paper presents a new Differential Cascode Voltage Switch Logic (DCVSL) design method which combines the differential logic design style with an analog current mirror. Compared to conventional DCVSL circuits, the proposed circuits have significant performance improvements with reduced switching latency. More importantly, our proposed circuits can successfully operate with low voltage supply, which is verified by the design the basic logic gates. We provide comparison results with conventional logic gates including AND/NAND, OR/NOR and XOR/NXOR to demonstrate the advantages of using our proposed design in terms of latency, power dissipation and area. With 1V supply voltage, 4ns signal period (250MHz), the simulated PDP is 7.86aWs for AND/NAND, OR/NOR gates, and 9.84aWs for XOR/NXOR gate, that is 51.67% and 24.31% performance improvement compared to the best case of conventional circuits.

Verification of security policies represents one of the most critical, complex, and expensive steps of modern SoC design validation. SoC security policies are typically implemented as part of functional design flow, with a diverse set of protection mechanisms sprinkled across various IP blocks. An obvious upshot is that their verification requires comprehension and analysis of the entire system, representing a scalability bottleneck for verification tools. The scale and complexity of industrial SoC is far beyond the analysis capacity of state-of-the-art formal tools; even simulation-based security verification is severely limited in effectiveness because of the need to exercise subtle corner-cases across the entire system. We address this challenge by developing a novel security architecture that accounts for verification needs from the ground up. Our framework, ArtiFact, provides an alternative architecture for security policy implementation that exploits a flexible, centralized, infrastructure IP and enables scalable, streamlined verification of these policies. With our architecture, verification of system-level security policies reduces to analysis of this single IP and its interfaces, enabling off-the-shelf formal tools to successfully verify these policies. We introduce a CAD flow that supports both formal and dynamic (simulation-based) verification, and is built on top of such off-the-shelf tools. Our approach reduces verification time by over 62X and bug detection time by 34X for illustrative policies.

In recent years, the size and complexity of digital circuits have grown drastically. Consequently, bugs may appear in a circuit in different phases of design and synthesis. If they remain undetected, they propagate to the physical chip and cause huge financial loss for the designers and manufacturers. Formal verification is an important task after design to ensure the correctness of a circuit. Recently, polynomial formal verification has gained special attention. If we prove that the space and time complexity of a verification method is polynomial, we can ensure that it is always scalable. Many digital circuits which are used in different applications have a tree-like structure. It has been proven that if a tree-like circuit is made of basic logic gates (AND, OR, NOT, NAND, and NOR), it can be verified polynomially using BDDs. However, these proofs cannot be extended to the general tree-like circuits containing XOR gates. In this paper, we propose a method to prove the correctness of a general tree-like circuit in polynomial time.