Synthesis from production-based specifications

This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters.

In this paper, a preliminary study using case-based teaching methodology in a digital IC design course is described. The proposed case-based course consists of ten lecture topics with hands-on labs and two projects. Each topic covers a design case example which contains illustrations of physical structure, hardware description language (HDL) codes, truth tables, waveform, and comments. Students can comprehend the essence of HDL by referring to physical logic gates, truth table, and waveform with HDL codes. This helps students to understand the abstract nature of HDL-based design flow especially for non-EE major undergraduates. To illustrate the effect of case-based teaching methodology instruction for non-major undergraduates, a specific class was constructed by 56% major and 44% non-major undergraduates. At the end of the course, both major and non-major undergraduates verified all labs and projects successfully. The questionnaire statistics show that most of the students like the course with case-based guidance. They all look forward to taking other similar engineering courses in the future.

This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a real-time hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

While online judge systems are widely used in programming related courses, they are rarely used in hardware-related courses such as the computer organization course requiring the digital circuit design. With the widely available FPGA hardware, students now have fewer difficulties in building hardware by only writing hardware description language (HDL) code. We have built a cloud-based lab environment that students can build CPUs online by submitting their Verilog HDL code. Our HDL online judge system is applied to test the submitted code. It greatly reduces the efforts of checking the code manually.

This paper presents the development of high level synthesis tools for finite impulse response (FIR) filtering application on the embedded system. A hardware description language (HDL) is used to describe the structure and behaviour of the electronic circuits and digital logic circuits. The HDL coder is a high level synthesis tool that converts the C/C++ files into.ngc files and then to generate bitstream. MATLAB is supported with Vivado in order to generate the MATLAB programming on FPGA board. Based on the least mean square (LMS) algorithm, FIR filter is developed by MATLAB generated with the HDL coder and compatible with FPGA hardware. Then, the developed algorithm is implemented and automated the verification of HDL code on Xilinx Zedboard for FIR filtering and planning including with the cost estimation and hardware usage. Simulation implementation show that the experimental results of adaptive LMS-FIR from MATLAB and Vivado can perform well for system identification.

The Field Programmable Gate Array (FPGA) offers opportunities for improved performance and design flexibility for digital control of power electronics. However, the complexity of Hardware Description Language (HDL) coding can be a barrier for the design engineer. Presented is a system modeling and development environment for FPGA-based digital control that also has the ability to auto-generate HDL code. The method uses Altera DSP Builder technology in a MATLAB / SIMULINK environment to develop a digital power electronics controller. A full-bridge PWM converter for a solar grid-tie inverter was built and close correlation to the model was demonstrated. The method presented provides complete system simulation of power electronics, while also providing the quality and productivity benefits of auto-code generation.

Performance Evaluation of Verilog Coding Techniques for Optimized MD5 Algorithm

In this paper a platform is presented, that given a stochastic context-free grammar (SCFG), automatically outputs the description of the parser in synthesizable hardware description language (HDL) which can be downloaded in an Field Programmable Gate Arrays (FPGA) board. Initially, according to our methodology the SCFG is augmented with attributes which store the probability values and can be evaluated through corresponding stack actions. The architecture of the produced system is based on a proposed extension of Earley’s parallel algorithm, which given an input string, generates the parse trees in the form of an AND-Or parse tree. This AND-or parse tree is then traversed using a proposed tree traversal technique in order to execute the corresponding actions in the correct order, so as to compute the necessary probabilities. The platform is suitable for embedded systems applications where a natural language interface is required or in pattern recognition tasks. The parser generated by the presented platform has been tested for various SCFGs and compared to software approaches. The performance comparison is one to two orders of magnitude in favor of the presented hardware, compared to previous software approaches, depending on the application, the input string length and the number of produced trees.

Fundamental principles of modeling timing in hardware description languages

Based on the material presented in Chap. 4, there are a few observations about logic design that are apparent. First, the size of logic circuitry can scale quickly to the point where it is difficult to design by hand. Second, the process of moving from a high-level description of how a circuit works (e.g., a truth table) to a form that is ready to be implemented with real circuitry (e.g., a minimized logic diagram) is straightforward and well-defined. Both of these observations motivate the use of computer aided design (CAD) tools to accomplish logic design. This chapter introduces hardware description languages (HDLs) as a means to describe digital circuitry using a text-based language. HDLs provide a means to describe large digital systems without the need for schematics, which can become impractical in very large designs. HDLs have evolved to support logic simulation at different levels of abstraction. This provides designers the ability to begin designing and verifying functionality of large systems at a high level of abstraction and postpone the details of the circuit implementation until later in the design cycle. This enables a top-down design approach that is scalable across different logic families. HDLs have also evolved to support automated synthesis, which allows the CAD tools to take a functional description of a system (e.g., a truth table) and automatically create the gate level circuitry to be implemented in real hardware. This allows designers to focus their attention on designing the behavior of a system and not spend as much time performing the formal logic synthesis steps that were presented in Chap. 4. The intent of this chapter is to introduce HDLs and their use in the modern digital design flow. This chapter will cover the basics of designing combinational logic in an HDL and also hierarchical design. The more advanced concepts of HDLs such as sequential logic design, high level abstraction, and test benches are covered later so that the reader can get started quickly using HDLs to gain experience with the languages and design flow.

We introduce a proof-carrying based framework for assessing the trustworthiness of third-party hardware Intellectual Property (IP), particularly geared toward microprocessor cores. This framework enables definition of and formal reasoning on security properties, which, in turn, are used to certify the genuineness and trustworthiness of the instruction set and, by extension, are used to prevent insertion of malicious functionality in the Hardware Description Language (HDL) code of an acquired microprocessor core. Security properties and trustworthiness proofs are derived based on a new formal hardware description language (formal-HDL), which is developed as part of the framework along with conversion rules to/from other HDLs to enable general applicability to IP cores independent of coding language. The proposed framework, along with the ability of a sample set of pertinent security properties to detect malicious IP modifications, is demonstrated on an 8051 microprocessor core.

The challenges posed by the Dark Silicon era, combined with the escalating computational demands of emerging applications, such as Deep Learning (DL), have strained the capabilities of traditional CPUs and GPUs, necessitating the development of Domain-Specific Accelerators (DSAs). Despite offering substantial enhancements in Power, Performance, and Area (PPA), DSAs encounter significant challenges, including the rapid evolution of applications that necessitate the frequent development of new architectures. This, coupled with the expertise-intensive nature of the design process, often leads to reduced flexibility and extended development cycles, ultimately hindering the broader adoption and efficient deployment of DSAs. To address these challenges, this paper introduces LLM-AID, an agile framework that streamlines the DSA design flow by transforming high-level abstract specifications into Hardware Description Language (HDL) code and facilitating backend Computer-Aided Design (CAD) tool operations. By synergistically combining Large Language Models (LLMs), High-Level Synthesis (HLS) tools, design exploration techniques, and symbolic AI, LLM-AID dramatically accelerates design iterations, optimizes hardware performance, and significantly reduces time-to-market. This innovative approach democratizes DSA development, empowering designers to achieve unprecedented productivity while delivering high-quality DSA solutions.

This paper uses the field-programmable gate array (FPGA) controller on air motor system. The proportional-integral (PI) and model reference adaptive control (MRAC) theories are actualized by the hardware description language (HDL) code. In circuit designs, modular conception is used to divide a complex system into many parts. This methodology reduces the development time and easy to debug for each module. In this research, the chip was produced by ALTERA company and LP-2900 FPGA design lab was produced by LEAP electronics. From experimental results, the chattering range was between the 0.6% and 1.8%. The FPGA speed controllers have good performance in air motor system.

An all-digital phase locked loop (A-DPLL)-based frequency synthesizer of the local oscillator (LO) for the radio frequency (RF) transceiver application such as in radio frequency identification (RFID) system has gained popularity among academia due to the transition of circuit technology from analog to digital implementation by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. The phase-frequency detector (PFD) is one of the main blocks in ADPLL and it is capable to detect the presence of phase and frequency errors by recognizing two input signals in digital form. The full-ranged of a time-to-digital converter (TDC) is commonly used in PFD block, but the power consumption is high. In this work, the less-TDC will be designed in the digital PFD block as an early development stage design for the ultra-low power ADPLL in order to improve fast phase-frequency acquisition and reduce power consumption. The digital PFD is designed by using Matlab Simulink and Verilog Hardware Description Language (HDL) code. The simulation result obtained that the time difference of the input signals for the Verilog is smaller than the result in Matlab Simulink without a unit delay. Thus, the design of the digital PFD will lead the desired ADPLL to achieve ultra-low power and fast locking range for RFID application.

The paper outline development and simulation of Pulse Interval Encoding (PIE) encoder architecture for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader based on Field Programmable Gate Array (FPGA). The PIE encoder architecture presented in this paper is according to International Organization for Standardization and International Electrotechnical Commission (ISO/IEC 18000-6) protocol. The behavior of the PIE encoder architecture is realized by derivation of Verilog Hardware Description Language (HDL) code in Quartus II software. Utilizing the ModelSim-Altera, the PIE encoder architecture is simulated to observe its functionality. The designing of the encoder is intended for uses in UHF RFID passive interrogator.