A proof-carrying based framework for trusted microprocessor IP

In this paper, a preliminary study using case-based teaching methodology in a digital IC design course is described. The proposed case-based course consists of ten lecture topics with hands-on labs and two projects. Each topic covers a design case example which contains illustrations of physical structure, hardware description language (HDL) codes, truth tables, waveform, and comments. Students can comprehend the essence of HDL by referring to physical logic gates, truth table, and waveform with HDL codes. This helps students to understand the abstract nature of HDL-based design flow especially for non-EE major undergraduates. To illustrate the effect of case-based teaching methodology instruction for non-major undergraduates, a specific class was constructed by 56% major and 44% non-major undergraduates. At the end of the course, both major and non-major undergraduates verified all labs and projects successfully. The questionnaire statistics show that most of the students like the course with case-based guidance. They all look forward to taking other similar engineering courses in the future.

This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a real-time hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

Modern Systems-on-a-Chip (SoC) are constructed by composition of IP (Intellectual Property) Cores with the communication between these IP Cores being governed by well described interaction protocols. However, there is a disconnect between the machine readable specification of these protocols and the verification of their implementation in known hardware description languages. Although tools can be written to address such a separation of concerns, such tooling is often hand written and used to check hardware designs a posteriori. We have developed a dependent type-system and proof-of-concept modelling language to reason about the physical structure of hardware interfaces respective to user provided descriptions. Our type-system provides correct-by-construction guarantees that the interfaces on an IP Core will be well-typed if they adhere to a specified standard.

This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters.

PANEL: analog intellectual property: now? or never?

While online judge systems are widely used in programming related courses, they are rarely used in hardware-related courses such as the computer organization course requiring the digital circuit design. With the widely available FPGA hardware, students now have fewer difficulties in building hardware by only writing hardware description language (HDL) code. We have built a cloud-based lab environment that students can build CPUs online by submitting their Verilog HDL code. Our HDL online judge system is applied to test the submitted code. It greatly reduces the efforts of checking the code manually.

This paper presents the development of high level synthesis tools for finite impulse response (FIR) filtering application on the embedded system. A hardware description language (HDL) is used to describe the structure and behaviour of the electronic circuits and digital logic circuits. The HDL coder is a high level synthesis tool that converts the C/C++ files into.ngc files and then to generate bitstream. MATLAB is supported with Vivado in order to generate the MATLAB programming on FPGA board. Based on the least mean square (LMS) algorithm, FIR filter is developed by MATLAB generated with the HDL coder and compatible with FPGA hardware. Then, the developed algorithm is implemented and automated the verification of HDL code on Xilinx Zedboard for FIR filtering and planning including with the cost estimation and hardware usage. Simulation implementation show that the experimental results of adaptive LMS-FIR from MATLAB and Vivado can perform well for system identification.

The authors describe a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant machine is derived from a hierarchy of sub-machine descriptions, each represented by a production. The production-based specification (PBS) consists of productions annotated with HDL action code, and forms the input to a design tool which outputs procedural HDL tailored for hardware synthesis. Due to the concise nature of this form of specification, the technique can save enormous labor in the construction of procedural specifications for these machines. Novel aspects of this research include the compilation of a PBS with HDL action clauses into synthesizable procedural HDL and the approach to specification of machine behavior in the event of exceptional conditions. >

The Field Programmable Gate Array (FPGA) offers opportunities for improved performance and design flexibility for digital control of power electronics. However, the complexity of Hardware Description Language (HDL) coding can be a barrier for the design engineer. Presented is a system modeling and development environment for FPGA-based digital control that also has the ability to auto-generate HDL code. The method uses Altera DSP Builder technology in a MATLAB / SIMULINK environment to develop a digital power electronics controller. A full-bridge PWM converter for a solar grid-tie inverter was built and close correlation to the model was demonstrated. The method presented provides complete system simulation of power electronics, while also providing the quality and productivity benefits of auto-code generation.

A WATM interface card using SOPC technology is presented in this paper. WATM is an extension of fixed ATM networks, and provides users wireless access to broadband services. The SOPC technology, developed by Altera Corporation, consists of a FPGA (field programmable gate array) and a Nios embedded processor. This paper introduces a novel method for design and implementation of WATM lower protocol layers. The new architecture of the card and the WATM access IP (intellectual property) is the main contribution of this work presented. The WATM access IP core, which is designed in Verilog HDL(Hardware Description Language), executes the function of WATM cell formatter and deformatter and checkout. The Nios embedded processor manages the execution of components in the access IP core. As a result, the use of SOPC technology can make the WATM interface card more compact, high performance and cost down.

The existence of hardware description languages (HDLs), the recent increase in performance, density and radiation tolerance of field programmable gate arrays (FPGAs), and intellectual property (IP) cores provides the technology for reprogrammable systems on a chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. To investigate the flexibility of this technology, the core of the central processing unit and input/output processor of the space shuttle AP101S computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

As digital microfluidic biochips (DMFBs) make the transition to the marketplace for commercial exploitation, security and intellectual property (IP) protection are emerging as important design considerations. Recent studies have shown that DMFBs are vulnerable to reverse engineering aimed at stealing biomolecular protocols (IP theft). The IP piracy of proprietary protocols may lead to significant losses for pharmaceutical and biotech companies. The micro-electrode-dot-array (MEDA) is a next-generation DMFB platform that supports real-time sensing of droplets and has the added advantage of important security protections. However, real-time sensing offers opportunities to an attacker to steal the biochemical IP. We show that the daisychaining of microelectrodes and the use of one-time-programmability in MEDA biochips provides effective bitstream scrambling of biochemical protocols. To examine the strength of this solution, we develop a SAT attack that can unscramble the bitstreams through repeated observations of bioassays executed on the MEDA platform. Based on insights gained from the SAT attack, we propose an advanced defense against IP theft. Simulation results using real-life biomolecular protocols confirm that while the SAT attack is effective for simple instances, our advanced defense can thwart it for realistic MEDA biochips and real-life protocols.

This paper proposes an improved procedure to watermark soft Intellectual Property (IP) Cores at the Register Transfer Level (RTL) using Genetic Algorithms (GA). In order to merge the watermark signature and the IP Core's behavioral description, both are translated into Finite State Machines (FSM). The resulting FSM contains the watermarked IP Core maintaining its original functionality without disruption. However, a set of hanging states (a group of states not deeply embedded) has been observed and if any of these is deleted, the watermark could be removed and possibly the original IP Core functionality would not be disrupted, allowing for copyright infringements. Thus, a reduction procedure is applied to the watermarked design to reduce the number of hanging states, which to the best of the authors' knowledge has not been developed. Both FSM merging and reduction are NP-Complete problems. In this study, an improved objective function is proposed to accurately model the FSM reduction problem while applying GAs as optimization techniques at both stages. Empirical results show a significant improvement in terms of the number of final hanging states and watermark embedding strength as regards previous reported approaches.

The paper describes verification of a 32-bit processor chip using formal reasoning. The VHSIC Hardware Description Language (VHDL) code for the processor and its components have been proven to meet the formal specification which uncovered interesting specification ambiguities and design errors. The paper provides an early evaluation of the role of formal reasoning in the verification of VHDL designs of practical size.

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.