PANEL: analog intellectual property: now? or never?

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

In the present era the increased complexity of design decreases the design cycle and reduces the cost. Efficient power consumption has led to the arrival of methodology of system-on-chip (SoC) in the semiconductor industry. A SoC usually contains reusable IPs, memory elements, bus architecture, that is for interfacing IPs, clock circuits and mixed signal blocks SRAM, that is embedded processors or controllers, and other components on SoC, programmable blocks, that is FPGA, and so on. The functionality of SoC can be easily improved by integrating more intellectual property (IP) components within it. A number of SoCs is integrated to form more complex system. Though the reuse of IPs on SoC has increased the hazard of misuse of IPs to the third-party entries, but it still plays an integral part of SOCs [1]. In silicon, IPP (industries IP protection) technique has been implemented in design flow of VLSI and has been extended to security considerations for SoC design methodology. In this paper the authors created IPs for Ethernet and HDMI using Xilinx Vivado 18.2, which is built for internet of things (IoT) application.

Since semiconductor intellectual property (IP) first emerged on the integrated circuit (IC) design scene over a decade ago, it has offered the promise of shaving months off of development time while allowing for the inclusion of many more functions in a design. At the heart of the problem is the need by IP providers to protect their development investment. Few IC designers can afford to pay the often high price for access to IP source code, so IP suppliers provide significantly less costly 'black box', or encrypted, versions for use with specific design tools. The problem with this is not only that the IP vendor is saddled with the cumbersome task of maintaining multiple IP core versions for various tool sets, but, more importantly, that it is an incomplete solution. To address the need for a means to protect IP from piracy while making it easier for the IF supplier to deploy and the IC designer to use, Synplicity has developed and introduced an open IP encryption/decryption methodology. It takes advantage of features in the most recent release of Verilog and commonly used encryption mechanisms in a new usage model that could become an industry standard.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

With the increasing complexity of system-on-chip (SoC) design, intellectual property (IP)-based design flow is becoming an inevitable trend to achieve high performance and short time-to-market. However the transfer of IP core remains a complex and time-consuming process. Different IP vendors usually use different design rules and tool flows, which make it difficult for IP integrators to select suitable IP cores and integrate them rapidly. In this paper, a common platform for IP qualification (CPIPQ) is presented to provide and establish a set of common standards to qualify Soft/Hard IP. There are two kinds of qualification methods: subjective quality metric and objective quality metric. We use IEEE QIP Metric to evaluate the subjective quality metrics of IP cores. Objective metrics are measured automatically by using commercial EDA tools, as well as tools that developed by ASTRI IC Design Group.

Intellectual properties (IPs) in design form are integrated for incremental design of system-on-chip (SoC). In order to realize proper functionality of an SoC, some global signal nets are often needed to be connected between the design IPs. If the component IPs are in-house, the global nets may be routed through the routing region of the design IPs and this routing may be formulated as an adaptive incremental routing problem where all the routing issues need to be tackled directly in the detailed routing phase only. In this work, we propose a technique for adaptive incremental routing of global nets with the objectives of minimal increase in wire length, congestion, and number of vias. The first objective maintains the desired frequency, the second and the third ones reduce the power overhead, and specifically the third one is effective in keeping the layout manufacture-friendly. The proposed technique is applied on some ISCAS’85 benchmarks and finally on a crypto SoC design which integrates several component designs for crypto-cores. The results on CPU time for routing and the overhead of routing are encouraging.

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Partial success has been achieved in deploying them. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of, design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. Another reason for the need to formalize is that, as designs become more complex, functional verification will have to be carried out using the divide and conquer approach.We discuss several approaches based on compositional verification. For these approaches to succeed, specifications of either, the individual modules, or individual IPs, if any are used, have to be stated formally. There exist several commercial offerings addressing the area of SoC functional verification. Most of these use some form of divide and conquer approach related to compositional verification. The basis of success of some of these tools lies in the fact that the specifications of the IP cores are in essence captured in some executable form, be they formal specification languages, or commonly used HDLs suitably modified for the purpose.This tutorial is structured to provide information on the state of the art in the area of functional verification. It will focus on existing methodologies, tools, and practical approaches based on universal simulation, emulation, formal verification, and semi-formal verification that can be employed to overcome the SoC verification problem. We discuss a number of real life verification projects, describing the various techniques used and the effectiveness of these techniques. We conclude the tutorial by presenting issues, which form the current focus for research.

The Case against Copyright: A Comparative Institutional Analysis of Intellectual Property Regimes

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP).Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 μm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to market, thus how to verify IP functionality on bus protocol is challenge. Traditional simulation-based bus protocol monitor scan check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule based bus protocol checker, it contain ns 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently Keywords: Arbiter, Reconfigurable, System-on-chip, Arbitration Algorithm, FPGA, AMBA

Modern Systems-on-a-Chip (SoC) are constructed by composition of IP (Intellectual Property) Cores with the communication between these IP Cores being governed by well described interaction protocols. However, there is a disconnect between the machine readable specification of these protocols and the verification of their implementation in known hardware description languages. Although tools can be written to address such a separation of concerns, such tooling is often hand written and used to check hardware designs a posteriori. We have developed a dependent type-system and proof-of-concept modelling language to reason about the physical structure of hardware interfaces respective to user provided descriptions. Our type-system provides correct-by-construction guarantees that the interfaces on an IP Core will be well-typed if they adhere to a specified standard.

With the development of chip design technology, the complexity of the chip is getting bigger and bigger, and various IP (Intellectual Property) is integrated to form SoC (System on Chip). In order to improve the efficiency of designing SoC, IP reuse technology is often used, so the development of IP has a wide range of significance and use value. The SPI bus is a bus protocol often used in chip communication and has many application scenarios. Therefore, this research mainly develops the SPI bus IP. During the development process, the SPI bus design is carried out, then based on the UVM verification methodology the designed IP has been functionally verified, and finally, a fully functional SPI bus design is obtained.

This paper introduces a multi-channels data synchronous acquisition and processing IP (intellectual property) core for digital protective relay. It integrates data acquisition and processing in one FPGA, resolving problem of asynchrony between data acquisition and data processing as well as setting of the number of sampling channels and sampling points per period. In contrast to the traditional acquisition system, it has characteristic of high speed, flexibility and low cost. This IP core was verified in FPGA (field programmable gate array) based hardware platform. The result of experiment indicates that this IP core is correct and can be used into SOC (system on chip) application as a single module.

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores

An IP (Intellectual Property) based SoC (System-on-Chips) is getting popular among designers as it allows for a faster development cycle for SoC production. However, each IP may use different bus interface causing compatibility issues during design integration. A WISHBONE bus and an AHB (Advanced High Performance Bus) are among commonly used bus interfaces for many IP cores. This paper describes the conversion operation from WISHBONE Bus protocol into an AHB bus protocol. This is to allow an Open RISC Micro Controller Unit (ORMCU), a master device which uses WISHBONE bus protocols, to communicate and control all other devices (slaves) that use AHB bus protocols. The design is a WISHBONE-to-AHB Bridge, which consist of a WISHBONE slave and an AHB master inside one module. The simulation results confirm that the bridge is able to handle communication from a WISHBONE master in an AHB system.