Verification of ASIC designs in VHDL using computer-aided reasoning

The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Although VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from initial concept through chip implementation were discussed, and one example of the process is discussed here. A Finite Impulse Response (FIR) filter was conceptually designed using the MATLAB programming environment to determine adequate performance specifications such as filter size and quantization levels. The design was then written using a behavioral VHDL coding style, as well as a VHDL test bench to determine if the VHDL behavioral model provided the same results as the MATLAB model. After design synthesis of the behavioral description using Synopys tools, the same test bench was used again to verify the performance of the structural VHDL netlist with annotated place and route delay information provided from the Alters MaxPluslI tools. Final verification took place with at the board level using an Altera CPLD programmed with the FIR filter design.

Chapter 1 - Introduction and Background

Modern digital system designs have been predominantly software driven, using the hardware description languages. While there are many different types of the hardware description languages, the most commonly used are VHDL (very high-speed integrated circuit hardware description language) and the Verilog. Both lend themselves to the successful realizations of the digital systems. However, even the experienced designers are often confused about which one to use and their relative performance characteristics. The authors discuss the general features of both languages from a design standpoint. Also, VHDL and Verilog based coding are discussed and the design realizations and simulations of the results are presented. We present the case studies of fundamental digital units such as full adders, comparators, counters and shift registers and discuss the timing and other important aspects which can be integrated into the actual designs. Also, the authors present a working model for hardware realizations using the CPLD (complex programmable logic device) platforms of the software designs. While it is acceptable to functionally check the designs with simulations, in actual applications, there is a need for hardware realizations as well. There are instances where the program code is sequential and the simulation results are also sequential. However, with the present complexity of CPLDs, and FPGAs where some hardware elements can be synthesized in concurrence, there can be timing problems. The authors also examine such instances and provide an insight into the arbitration schemes for a reliable digital system realization.

The design of increasingly more complex custom and semicustom integrated circuits has traditionally forced the introduction of new design methodologies. Formal specifications, top-down design, and design-for-test have become standard practices for IC design teams. The adoption of VHDL (VHSIC Hardware Description Language), as an IEEE standard (IEEE-1076), and the recent availability of design automation tools supporting VHDL, has begun yet another wave of change in the ASIC design process. The author investigates the impact of VHDL on the ASIC design team, as well as on the ASIC manufacturer. It is his intention to identify areas which must be investigated by the ASIC community before incorporating VHDL in the design process. >

Correlation has a variety of applications that require signal processing. However, it is computationally intensive, and software correlators require high-performance processors for real-time data analysis. This is a challenge for embedded devices because of the limitation of computing resources. Hardware correlators that use Field Programmable Gate Array (FPGA) technology can significantly boost computational power and bridge the gap between the need for high-performance computing and the limited processing power available in embedded devices. This paper presents a detailed FPGA-based correlator design at the register level along with the open-source Very High-Speed Integrated Circuit Hardware Description Language (VHDL) code. It includes base modules for linear and multi-tau correlators of varying sizes. Every module implements a simple and unified data interface for easy integration with standard and publicly available FPGA modules. Eighty-lag linear and multi-tau correlators were built for validation of the design. Three input data sets—constant signal, pulse signal, and sine signal—were used to test the accuracy of the correlators. The results from the FPGA correlators were compared against the outputs of equivalent software correlators and validated with the corresponding theoretical values. The FPGA correlators returned results identical to those from the software references for all tested data sets and were proven to be equivalent to their software counterparts. Their computation speed is at least 85,000 times faster than the software correlators running on a Xilinx MicroBlaze processor. The FPGA correlator can be easily implemented, especially on System on a Chip (SoC) integrated circuits that have processor cores and FPGA fabric. It is the ideal component for device-on-chip solutions in biosensing.

The VHDL Design Exchange Group (VDEG), which consists of VHDL (VHSIC hardware description language) suppliers and users, was formed to promote the identical operation of VHDL models on different tools. One task of VDEG, which is still ongoing, is to develop a consensus logic model and a method for its use. VDEG and the VDEG's work on this task as of September 1989 are described. The definition of portability used by VDEG and the minimalist approach toward a standard multivalue logic type for modeling favored by the group are examined. The use of the model is discussed. VDEG is developing a library of packages to aid in the construction of portable models; the package containing definitions of types of operations is described in some detail. Two mappings are presented to illustrate the assertion that the portable logic model is easy to map to the logic models in existing tools. Future work is outlined. >

This paper specializes in developing a real-time faults classification system powered by phasor estimation and supervised learning algorithms. The classification system is embedded in a low-cost Field-Programmable Gate Array (FPGA) programmed using VHSIC Hardware Description Language (VHDL) code, exploiting the flexibility in its parallel architecture and real-time execution that imply faster processing speeds than microcontrollers. The phasor estimation is driven by a nonrecursive Discrete Fourier Transform (DFT) and the supervised learning-based classifier model is conducted by a Support Vector Machine (SVM). Experimental tests corroborate the system performance and its reliability under different fault conditions.

Induction motors are currently used in many industrial applications. Thus, their control techniques have received a lot of interest. An efficient method of induction motor control is the Direct Torque Control (DTC). It is considered particularly interesting since it is independent of machine rotor parameters and requires no speed or position sensors. This paper presents a simulation of a DTC strategy for three-phase induction motors based on the Field Programmable Gate Array (FPGA) technology. The real controller is not experimentally tested. A specific methodology for the hardware description language in VHSIC Hardware Description Language (VHDL) is presented. This paper summarizes the prior work before implementing the experimental FPGA control of an induction motor. This methodology allows one to verify the behavior of the VHDL codes before their implementation, reducing the risks of significant changes when implemented. The VHDL design technique for DTC-based speed control is designed through the descriptions of coordinate transformation, speed controller, stator flux and torque estimator, stator flux and torque controller, and stator flux position detector. The simulation is performed using the MATLAB/Simulink, DSP Builder, and Quartus II software, on an Altera DE2-115 board. Simulation results verify the validity of the proposed method.   Key words: Digital control, induction motor, digital signal processing, VHSIC Hardware Description Language (VHDL).

Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the design flow representation with the particular view on VHDL is presented. It is a three-dimensional cube with three coordinates divisions per dimension. Each state of the cube represents a modeling style in VHDL. For the use of more powerful hardware description languages, the cube may be extended to four coordinates per dimension. >

This paper presents the design of traffic controller hardware using fuzzy expert system algorithm for traffic light controlling purpose. The process uses the knowledge base of a Fuzzy System - rule base and parameters. This knowledge based system aspect makes the design more simple and efficient, especially when compared with traditional trial and error methods. A functional Fuzzy Traffic Controller (FTC), which utilises fuzzy logic algorithm to achieve a smart and a flexible knowledge-based system in hardware design while achieving better efficiency in the traffic control and minimizing traffic jam occurrences at interchange on road area. We describe a hardware platform for evolving system by using knowledge base of a Fuzzy System. To develop the system, the behaviour level of FTC algorithm has developed using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) under MAX+PLUS II CAD environment. The Finite State Machine (FSM) of the FTC has been coded in VHDL program for controlling the specific traffic flow application. Later on, the FPGA Express (Synthesis tool) has used to get a fully gate level synthesis architecture for the whole Fuzzy based hardware chip. The designed codes of the FTC have downloaded onto the UP1 FPGA (Field Programmable Gate Array) Educational board (Altera FLEX10K) for verifying the FTC hardware chip functionality. The performance of an expert fuzzy system based chip for controlling traffic light is evaluated.

IEC 61499 runtime systems to-date have focussed on software implementations deployed to various micro-processors. This study proposes a novel and viable architecture allowing IEC 61499 models to be deployed as custom logic within a field programmable gate arrays (FPGAs). A complier/translator has been developed, by the authors, capable of translating IEC 61499 models to their very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) equivalent in accordance with this architecture. This architecture, and the associated compiler/translator, thus facilitates an exploration of the runtime behaviour of IEC 61499 elements in the context of FPGAs. This study also reports on a case study that was performed on a specific test scenario to determine the suitability and performance of the described architecture and associated compiler/translator. It was thus found that deploying IEC 61499 models to FPGAs allows capitalising on the parallel execution capabilities of the FPGA, resulting in the ability to handle simultaneous events and to execute algorithms in parallel. It was also found that simple modifications to the architecture result in a more traditional sequential behaviour. Furthermore, the architecture is capable of delivering highly deterministic hard real-time implementations of IEC 61499 models.

A methodology1 that efficiently translates Estelle formal specifications into a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) description, suitable for the high level syntesis of an integrated circuit, is proposed. It will be shown that, in order to efficiently map Estelle into VHDL, a number of constrains must be imposed on the set of possible constructs within each language. An example based on the specification of a high speed protocol is discussed.

A scheme for the automatic verification of models described in VHDL (the VHSIC hardware description language) is proposed. For models with many constraints it becomes exceedingly difficult to verify their validity. In the proposed scheme the specifications for the system, i.e. the timing constraints and relations between the inputs and outputs, are described by the designer in modified linear time temporal logic, which is an extension of traditional logic and can describe timing relations among variables. Tests and simulations are conducted on the model described in VHDL, based on the given specifications. The outputs of the simulations are evaluated and compared with expected results. Discrepancies from the given specifications are reported. >

VHSIC hardware description language (VHDL) is a very rich and flexible language, which offers large possibilities in the simulation domain. The current state of the art of the formal proof technique does not enable handling all these possibilities. It applies only to synchronous descriptions. The author proposes definitions of the main object semantics to be used in a synchronous description. The resulting VHDL guidelines are described. These make up the bases of a VHDL subset suitable for formal proof and also for synthesis tools. >

We present an algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.