Synthesising an asynchronous DMA controller with Balsa

SummaryIn this article, an asynchronous adaptive tracking control approach is presented for a type of hidden Markov jump nonlinear systems with external disturbances. In this joint jump process model, hidden Markov model signifies the dynamics of the actual system, whereas the signal emits from the detector symbolizes the transmitted information. This leads to the phenomenon of asynchronization between the modes of the system and that of the controller. Accordingly, an asynchronous observer is developed by using the mode information from the detector to develop an asynchronous control approach. The observer contains a disturbance estimation part, to compensate the unknown external inputs. Utilizing the backstepping scheme, a strict‐feedback asynchronous tracking controller is formulated, guaranteeing that all signals within the closed‐loop system are semi‐globally uniformly ultimately bounded in probability. Finally, the validity of the presented methodology is illustrated by means of a simulation example.

This paper introduces a new scan control technique to realize low area overhead of scan-latches. Single transparent-latch is popularly used for register of high-throughput datapaths. For the scan-test of those kind of circuits, each transparent-latch is replaced with scan-latch. Conventional scan-latch cells controlled by synchronous signals consist of L1 latch and additional L2 latch, both of which function as master latch and slave latch respectively in scan mode. Apparently, additional L2 latch may result in area overhead. In order to avoid the area impact of such an additional L2 latch, we propose new timing methodology employing asynchronous control technique asP* protocol, and introduce asynchronous controlled scan-paths whose scan-latch employs only L1 latch. We evaluate the operation speed with HSPICE simulations and see they are practical. We also suggest DFT structure with our suggested asynchronous scan-paths, which is suitable for conventional synchronous test systems.

This paper is concerned with the asynchronous dissipative control for discrete-time singular Markov jump systems with multiplicative noises. In a real set, noises always exist in the state or output measurement, which may cause some errors and decrease system performance. Without loss of generality, both state and output multiplicative noises are considered in this paper. The singular systems, which could widely describe more general systems and present traits of physical features, are discussed in this paper. Using a Markov chain to model the asynchronous jumps existing in system modes and controller modes. Through a method of LMI, the sufficient conditions are derived and the asynchronous controller is designed to ensure that the singular Markov jump systems are stochastically admissible and strictly dissipative.

In recent years, the problems of asynchronous control and filtering for Markov jump systems (MJSs) have received great research attention from scientific and engineering communities. The asynchronous situation between the original MJSs and the controller/filter is modelled by the hidden Markov model (HMM). This work gives a survey on the recent development of the HMM-based asynchronous controller and filter design for different MJSs, covering linear MJSs, fuzzy MJSs, semi-MJSs and 2D MJSs. Finally, a conclusion is drawn and the potential future research directions of MJSs are also discussed.

This paper presents a novel design method for asynchronous control logic targeting successive approximation register (SAR) analog-to-digital converters (ADCs). This work is based on modeling the control logic for SAR ADCs using signal transition graphs (STGs). Different from conventional synchronous controllers, the proposed method results in asynchronous controllers driven by the causality of signals rather than relying on clocks to control the conversion process. Moreover, the proposed asynchronous control logic can be modularized through the handshake protocol, making it possible to build ADCs of arbitrary precision based on single-bit control units. This work results in a formal, model-based asynchronous design flow for SAR ADC control, which is shown to produce resulting circuits of similar speeds but great power efficiency improvements.

The paper concerns the problem of reliable dissipative asynchronous controller design for a type of stochastic Markov jump systems (MJSs) with general conditional probabilities in the presence of the dynamic event-triggered rule. Since the mode information of the stochastic MJS is impossible to obtain, a reliable asynchronous controller is established such that the phenomena of nonsynchronous modes between the original stochastic MJS and the developed controller is formulated as a hidden Markov model. A novel dynamic event-triggered strategy is constructed to further decrease the data transmission frequency over the communication network. By taking the internal dynamic variable into account, the criteria of stochastically stable with the reliable dissipativity performance for the resulting closed-loop stochastic MJS are provided based on a collection of linear matrix inequalities. Further, the designs of reliable dissipative asynchronous controller and the dynamic event-triggered strategy are developed simultaneously. Lastly, a numerical instance is supplied to elucidate the superiority of proposed method.

In this note, the guaranteed cost control problem for discrete-time Markovian jump systems with state and input multiplicative noise is solved. Since the model mismatch problem often exists in system modes and controller modes, an asynchronous controller is presented to make the system stochastically stable. By using of the linear matrix inequality techniques, an optimization solution can be obtained, such that the quadratic cost function can be minimized, meanwhile the expectation of the state and control can be guaranteed in a constraint set.

In this article, the issue of dissipative asynchronous control for continuous-time T–S fuzzy singular Markov jump linear parameter-varying systems against dual deception attacks under the dynamic event-triggered transmission protocol (DETP) is investigated. Firstly, the DETP is offered to further abate the channel congestion caused by the limited bandwidth. Meanwhile, the mutually independent random variables subject to Bernoulli distribution are utilized to model the dual deception attacks, which can destroy the integrity of the considered system to some degree. Besides, since the controller can not accurately receive the system information, a hidden Markov model is established to depict the asynchronous phenomenon. Specifically, in the light of the parameter-dependent Lyapunov functional, the stochastic admissible criterion of the closed-loop system with certain dissipative performance and uncertain transition rates is obtained. Ulteriorly, based on the parameter-dependent linear matrix inequalities, a cooperative design technique of asynchronous controller and the weighting matrix of the DETP is proposed. Finally, two examples of chaotic systems and electric truck-trailer systems under the DETP are given to illustrate the feasibility of the proposed method.

This article addresses the dissipativity-based asynchronous repetitive control problem for networked Markovian jump systems subject to time delays and partly accessible mode detection probabilities. A hidden Markov model is introduced to describe the asynchronous phenomenon between the system modes and controller modes. Based on this, an asynchronous repetitive controller is proposed. By utilizing the lifting technique, the 1-D delayed Markovian jump system and controller governing equations are converted into a stochastic and closed-loop 2-D delayed model to describe the control and learning actions. Utilizing a stochastic Lyapunov functional, sufficient conditions in terms of matrix inequalities are derived such that the closed-loop system is mean-square stable and achieves the specified (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) -γ-dissipative performance. Under the assumption that the input matrix is full column rank in all modes of operation, a set of feasible sufficient conditions described by linear matrix inequalities is established by making use of the Schur complement. A procedure for synthesizing the controller parameters is also provided. A detailed numerical example with simulation results is presented to validate the proposed dissipativity-based asynchronous repetitive control design scheme.

Finite-time synchronization for coupled neural networks with time-delay jumping coupling

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

This paper investigates an innovative technology for asynchronous fuzzy preview control (FPC) in nonlinear Markov jump systems (MJS) with time-varying uncertainties and partly unknown transition probabilities using the Takagi-Sugeno (T-S) fuzzy model. It is assumed that the system modes cannot be obtained synchronously by the controller, but instead there is a detector that provides estimated values of the system modes. The proposed asynchronous FPC strategy depending on the detector mode considers time-changing uncertainties and previewable target signals. The asynchronous controller integrates a fuzzy feedback controller, a fuzzy preview controller, and an integrator to address the tracking control problem of target signals. The research constructs a T-S fuzzy augmented error model (AEM) using the error system method and state augmentation technique. Subsequently, the asynchronous FPC design challenge is transformed into a feedback stabilization problem of the AEM. Employing Lyapunov function and LMI techniques, the study derives sufficient conditions for the stability of the AEM in the form of a set of LMIs, presenting the design method of the asynchronous FPC law. The validity of the results is demonstrated through numerical simulations.

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

This paper investigates the asynchronous event-triggered state-feedback control for discrete-time nonlinear singular Markov jump systems subject to reachable set bounding and stochastic cyber-attacks. An event-triggered mechanism is introduced to regulate data transmission and save network resources. While this mechanism brings advantages, it also causes that the mode information of the system and the controller are not synchronized. On the other hand, network communication has brought convenience to signal transmission, and it has also resulted in the network channel being in an open and unreliable environment, which is vulnerable to cyber-attacks. In order to solve these problems, the secure asynchronous controller is designed to effectively resist the influence of attacks. In addition, by using the reachable set analysis approach, the constructed controller ensures that the estimation error is within the boundary of the ellipsoid, and the existence conditions of the required controller are given by solving the linear matrix inequalities. Finally, a simulation example is given to illustrate the effectiveness of the theoretical results.

In sequential circuits, the current output can depend on both past and current inputs. However, certain kinds of sequential circuits do not refer to all of the past inputs to generate the current output; but only to a subset of past inputs. This paper investigates which subset of past inputs a sequential circuit refers to, and proposes a new classification of sequential circuits based on this criterion. While the conventional classification of sequential circuits distinguishes between synchronous and asynchronous circuits, the new classification consolidates synchronous circuits and multiple clock domain circuits into the same category. This is consistent with the notion that “multiple clock domain circuits are analogous to synchronous circuits,” and thus, the proposed classification appears valid from this perspective. It is expected that a method underlying our classification will allow a deeper understanding of sequential circuits.