System-level MP-SoC design space exploration using tree visualization

The factors that influence product development depend, amongst other things, on the type of product, the economic situation, the state of the art technology and various social and cultural trends. In modern era, often not the specs and costs are the decisive factors for purchasing a product, but aspects like design and brand personality. One of the reasons for this is the abundance of products of the same type for the same purpose. In fact, this is the current situation for dry powder inhalers (DPIs) although the self-congruity concept seems more applicable to the doctors who prescribe the inhalers than to the patients who are using them. For the early DPIs from the 1960s and 1970s the driving factor for development was the necessity of having an alternative for cholofluorocarbon (CFC) containing metered dose inhalers (MDIs). An important factor affecting their design could have been the desire to improve pulmonary drug delivery compared to that from MDIs, but unfortunately this oportunity was missed. Instead, available technology like hard gelatin capsules and adhesive ('ordered') mixtures were used and lung deposition remained more or less the same as from MDIs (only approx. 10% of the dose). After the capsule (and multi-dose reservoir) DPIs became more widely accepted and patents on inhaled drugs expired, consulting groups and generic manufacturers became more and more involved in the emerging DPI market, purely on an economic basis. This does not mean that there have not been developments yet aiming at improvement of the therapy with DPIs and various future applications may give a new boost to using new technology for dry powder inhalation.

The hardware design space is high-dimensional and discrete. Systematic and efficient exploration of this space has been a significant challenge. Central to this problem is the intractable search complexity that grows exponentially with the design choices and the discrete nature of the search space. This work investigates the feasibility of learning a meaningful low-dimensional continuous representation for hardware designs to reduce such complexity and facilitate the search process. We devise a variational autoencoder (VAE)-based design space exploration framework called VAESA, to encode the hardware design space in a compact and continuous representation. We show that black-box and gradient-based design space exploration algorithms can be applied to the latent space, and design points optimized in the latent space can be reconstructed to high-performance realistic hardware designs. Our experiments show that performing the design space search on the latent space consistently leads to the optimal design point under a fixed number of samples. In addition, the latent space can improve the sample efficiency of the original algorithm by 6.8$\times$ and can discover hardware designs that are up to 5% more efficient than the optimal design searched directly in the high-dimensional input space.

The organic Rankine cycle (ORC) system can effectively recover waste heat from engines of heavy‐duty trucks, and is a promising method to improve the efficiency of on‐board engines. However, engine operating conditions fluctuate greatly while driving, the waste heat recovery system must often work under off‐design conditions, which significantly affects system performance. Further, different component structures can also affect the off‐design performance of the system. Thus, a novel design method of preheating organic Rankine cycle (P‐ORC) system harvesting waste heat of heavy‐duty trucks based on off‐design performance is proposed in this study. The design method includes selection of the optimal types of components and design point to optimize the comprehensive performance of the waste heat recovery system in all road conditions. In this study, different heat exchanger combinations are applied to the P‐ORC system to obtain six different design systems. According to the principle of uniform coverage, the scatter diagram of exhaust temperature and mass flow rate of the engine under real road conditions are discretized into 19 alternative design points. Each system is designed with 19 discretized design points, and a total of 114 design systems are obtained. The optimal heat exchanger combination and design point are selected based on the off‐design performance. It is concluded that a P‐ORC system using a combination of plate preheater, finned tube air cooler, and shell‐tube evaporator is the optimal system. The optimal design point number is 10, and the corresponding engine speed at is 1471 rpm, the engine torque is 474 Nm, the occurrence probability is 14.48%, the exhaust temperature is 350°C, the exhaust mass flow rate is 0.11 kg/s, and the maximum combined net power output is 4.26 kW. The results reveal that the optimal design point of the system can be selected at the design point with medium engine load and high occurrence probability. It guides the system design toward a more practical direction, so as to obtain an optimal system that could operate efficiently and recover more waste heat under the full working conditions of the engines. This novel design method can be extended for other cycle configurations.

This study describes the use of an analytical model, constructed using sequential design of experiments (DOEs), to optimize and quantify the uncertainty of a Diesel engine operating point. A genetic algorithm (GA) was also used to optimize the design. Three engine parameters were varied around a baseline design to minimize indicated specific fuel consumption (ISFC) without exceeding emissions (NOx and soot) or peak cylinder pressure constraints. An objective merit function was constructed to quantify the strength of designs. The engine parameters were start of injection (SOI), injection duration, and injector included angle. The engine simulation was completed with a sector mesh in the commercial computational fluid dynamics (CFD) software CONVERGE, which predicted the combustion and emissions using a detailed chemistry solver with a reduced mechanism for n-heptane. The analytical model was constructed using the SmartUQ software using DOE responses to construct kernel emulators of the system. Each emulator was used to direct the placement of the next set of DOE points such that they improve the accuracy of the subsequently generated emulator. This refinement was either across the entire design space or a reduced design space that was likely to contain the optimal design point. After sufficient emulator accuracy was achieved, the optimal design point was predicted. A total of 5 sequential DOEs were completed, for a total of 232 simulations. A reduced design region was predicted after the second DOE that reduced the volume of the design space by 96.8%. The final predicted optimum was found to exist in this reduced design region. The sequential DOE optimization was compared to an optimization performed using a GA. The GA was completed using a population of 9 and was run for 71 generations. This study highlighted the strengths of both methods for optimization. The GA (known to be an efficient and effective method) found a better optimum, while the DOE method found a good optimum with fewer total simulations. The DOE method also ran more simulations concurrently, which is an advantage when sufficient computing resources are available. In the second part of the study, the analytical model developed in the first part was used to assess the sensitivity and robustness of the design. A sensitivity analysis of the design space around the predicted optimum showed that injection duration had the strongest effect on predicted results, while the included angle had the weakest. The uncertainty propagation was studied over the reduced design region found with the sequential DoE in the first part. The uncertainty propagation results demonstrated that for the relatively large variations in the input parameters, the expected variation in the ISFC and NOx results were significant. Finally, the predictions from the analytical model were validated against CFD results for sweeps of the input parameters. The predictions of the analytical model were found to agree well with the results from the CFD simulation.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

Design space exploration of microprocessor is still a challenging task for processor designers. Due to the huge design space, it is hard to determine the optimal configuration of microarchitecture parameters to satisfy the target performance and power requirements within limited time at the early stage of processor design. In this paper, a Critical Path Analysis directed Design Space Exploration (CPADSE) methodology for design space exploration of microprocessors is proposed. In CPADSE, a dependence graph model is constructed using the profile information generated during the program simulation. Then the critical paths of the dependence graph model are computed and patterns of the critical path are identified. The microarchitecture parameters mostly affecting processor`s performance or other metrics can be identified using the Plackett-Burman design method, which is always referenced as sensitivity analysis. Then the result of critical path analysis and sensitivity analysis is further used to guide the selection of search direction in both SA-CPADSE and TB-CPADSE design space search algorithms, which are proposed in this paper. Experiment result shows that for the design space exploration on SPEC 2000 benchmarks, SA-CPADSE obtains 2x speedup over baseline design space exploration algorithm SA-DSE. Additionally, TB-CPADSE on average obtains 4.3x speedup over SA-CPADSE and 7x speedup over SA-DSE. At the end of this paper, we have a detailed discussion about how to extend CPADSE methodology to design space exploration of multicore processors.

Exploration with a generative formalism must necessarily account for the nature of interaction between humans and the design space explorer. Established accounts of design interaction are made complicated by two propositions in Woodbury and Burrow's Keynote on design space exploration. First, the emphasis on the primacy of the design space as an ordered collection of partial designs (version, alternatives, extensions). Few studies exist in the design interaction literature on working with multiple threads simultaneously. Second, the need to situate, aid, and amplify human design intentions using computational tools. Although specific research and practice tools on amplification (sketching, generation, variation) have had success, there is a lack of generic, flexible, interoperable, and extensible representation to support amplification. This paper addresses the above, working with design threads and computer-assisted design amplification through a theoretical model of dialogue based on Grice's model of rational conversation. Using the concept of mixed initiative, the paper presents a visual notation for representing dialogue between designer and design space formalism through abstract examples of exploration tasks and dialogue integration.

This paper describes a novel and fast placement algorithm for FPGA design space (e.g., area, power or reliability) exploration. The proposed algorithm generates the placement based on the topological similarity between two configurations (netlists) in the design space. Thus, it utilizes the sharing of reusable information during the design space exploration and avoids the time-consuming placement computation like VPR. Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the “shape” of a design space and pinpoints the designs which are of most interest to IC designers. Moreover, a turbo version of circuit similarity-based placement performs an average of 30x (up to 100x) faster than VPR's while still achieving comparable placement results.

A major challenge in the model‐based engineering of Cyber‐Physical Systems (CPSs) is that of providing methods and tools that support decision‐making in design. In the CPS design space, system models may be composed of diverse notations and tools, and the range of alternatives to be evaluated is immense. In spite of this, the benefits of trade‐off analysis at an early design stage are significant, making the automation of Design Space Exploration (DSE) an appealing prospect. In bringing DSE to industry scale, there is a clear need for both guidance to engineers in designing DSE, and a theory of cost‐effective DSE algorithms. To address this, we propose and demonstrate a SysML profile that encourages the explicit description of DSE over multi‐disciplinary co‐models, and demonstrate the ability to tune a genetic DSE algorithm across a range of design spaces.

Exploration of a design space is the first step in identifying sets of high-performing solutions to complex engineering problems. For this purpose, Bayesian network classifiers (BNCs) have been shown to be effective for mapping regions of interest in the design space, even when those regions of interest exhibit complex topologies. However, identifying sets of desirable solutions can be difficult with a BNC when attempting to map a space where high-performance designs are spread sparsely among a disproportionately large number of low-performance designs, resulting in an imbalanced classifier. In this paper, a method is presented that utilizes probabilities of class membership for known training points, combined with interpolation between those points, to generate synthetic high-performance points in a design space. By adding synthetic design points into the BNC training set, a designer can rebalance an imbalanced classifier and improve classification accuracy throughout the space. For demonstration, this approach is applied to an acoustics metamaterial design problem with a sparse design space characterized by a combination of discrete and continuous design variables.

Universal design space exploration for building energy design

Methods for evaluating and covering the design space during early design development

The design space exploration (DSE) of fault-tolerant multiprocessor systems is very complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task mapping; and 3) task scheduling. In addition, replication-based task hardening can introduce new tasks, called replicas, into the system, enlarging the design space further. As a population-based global optimization algorithm, evolutionary algorithms (EAs) have been widely used to explore this huge design space over the last decade. However, as analyzed in this paper, the search space of previous works is highly redundant, resulting in poor efficiency and scalability. This paper proposes an efficient EA-based DSE method for the design of large-scale fault-tolerant multiprocessor systems. The main novelties of this paper include: 1) mapping exploration is explicitly separated, i.e., task mapping is optimized during the evolutionary search, while replica mapping is constructed heuristically according to the current co-synthesis state; 2) the design space of task hardening and task mapping are explored independently by a cooperative co-EA; and 3) as a complement to global search of EA, problem-specific local search operators are designed for both task hardening and task mapping, reducing the number of fitness evaluations required. Compared with the most relevant state-of-the-art method, the superiority of the proposed method is demonstrated using extensive experiments on a large set of benchmarks, e.g., 1.75×~2.50× better results can be obtained on the benchmarks of 300 tasks and 30 processors.

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform

The complexity of state-of-the-art processor architectures and their consequent vast design spaces have made it difficult and time-consuming to explore the best configuration for them. Design space exploration (DSE) refers to systematic analysis and pruning of unwanted design points based on parameters of interest. DSE requires analysis and estimation of performance criteria of design points. A more accurate estimation produces a more efficient target design. A typical estimation method is machine learning approaches based on statistical inference, also known as empirical modeling, which requires only a limited number of simulations. Undoubtedly, an empirical model finds the optima much faster than using cycle-accurate simulations and is much more accurate than employing analytical models. For that purpose, our paper proposes a general methodology and a framework to find an appropriate and most accurate empirical model to estimate the performance of general-purpose or embedded multiprocessors running multithreaded workloads. This framework consists of three main steps: (1) Workload characterization and clustering, (2) Finding optimal model, and (3) Estimating the performance of a new workload outside the training set. These optimal performance prediction models could be utilized in the process of exploring the architectural design space. An experimental case is also tested using this framework for feasibility purposes. Validation experiments show MAEs less than 10% for this case.