Systematic co-optimization from chip design, process technology to systems for GPU AI chip

In recent year, based on high performance computing (HPC) and big data computing (BDC) application need to upgrade these performance incudes high process rates, high communication rate and low latencies. As transistor scaling reaches physical and economic barriers, the performance and cost of transistors are increasingly lagging behind the historical Moore's Law trajectory. Heterogeneous integration of SiP (system in package), 2.5D and fan-out solutions are driving the beyond Moore vision. In this paper, it is demonstrated that one of fan-out technology is to provide the high RDL layer count and fine RDL line width and line space, called FO-MCM (fan-out multi-chip modules). The FOMCM used organic interposer is applied lower RC delay and the high I/O density interconnection for HBM dies integration in comparison to 2.5D with the whole piece of Si interposer. Since HPC and BDC application performance derived High Bandwidth Memory grow up, that also impact the assembly package structure in parallel. The next general HBM need more metal layers to keep the performance in high frequency compare to original package design. SPIL's FO-MCM development integrates chips by 1 ASIC die and 2 HBM with 4–6 layers RDL show in Fig. 1. Since FOMCM used organic interposer to bridge chips, this kind of package can provide the solution which is cheaper than 2.5D and has simply vendor management to the end customer. As such, an overview of Fan-out integration solution associated with HBM will be presented in this paper.

With the development of peta- and exascale size computational systems there is growing interest in running Big Data and Artificial Intelligence (AI) applications on them. Big Data and AI applications are implemented in Java, Scala, Python and other languages that are not widely used in High-Performance Computing (HPC) which is still dominated by C and Fortran. Moreover, they are based on dedicated environments such as Hadoop or Spark which are difficult to integrate with the traditional HPC management systems. We have developed the Parallel Computing in Java (PCJ) library, a tool for scalable high-performance computing and Big Data processing in Java. In this paper, we present the basic functionality of the PCJ library with examples of highly scalable applications running on the large resources. The performance results are presented for different classes of applications including traditional computational intensive (HPC) workloads (e.g. stencil), as well as communication-intensive algorithms such as Fast Fourier Transform (FFT). We present implementation details and performance results for Big Data type processing running on petascale size systems. The examples of large scale AI workloads parallelized using PCJ are presented.

Technological progress, especially in the field of information, has led to reducing the gap between science, information and knowledge. This accelerating change has forced all educational institutions to comply with this new mission by using information technology in the teaching process, as artificial intelligence has become an integral part of the educational and learning process, and a means of Effective in the teaching process, in addition to being research tools in obtaining information and knowledge, the research problem focused on (what are the attitudes of the kindergarten teacher towards using artificial intelligence applications in the effective teaching process in the early education stage in the third Rusafa Education Directorate?), where the importance of The research is considered one of the researches that deals with an important and vital topic (artificial intelligence), as it gains its importance in that it represents the role that kindergarten teachers play in the early education stage in developing the skills and abilities and refining the information of the child through their use of artificial intelligence methods and applications, as well as The positive role of such research in stimulating kindergarten teachers’ motivation to benefit from artificial intelligence applications, which increases the efficiency and effectiveness of their teaching. The aim of the research is to reveal kindergarten teachers’ attitudes towards using artificial intelligence in the effective teaching process in the early education stage, as well as to reveal the most important The challenges facing kindergarten teachers using artificial intelligence in the effective teaching process, and are there any statistically significant differences between the average kindergarten teacher’s attitudes to using artificial intelligence in the effective teaching process in the early education stage according to the research variables? The research reached several conclusions, perhaps the most important of which is the existence of differences. There is statistical significance between the average kindergarten teacher’s attitudes to using artificial intelligence in the effective teaching process in the early education stage according to the research variables. The research recommends holding many workshops and training courses for kindergarten teachers on how to use artificial intelligence in effective teaching, and including programs and rehabilitation plans for kindergarten teachers. About the use of artificial intelligence according to the plans of the Ministry of Education, which are consistent with its vision, and encouraging teachers to proceed and benefit from applications and websites for safe and available artificial intelligence applications in the teaching process

In high performance computing (HPC) applications, the speed of the L1 cache will typically determine the maximum frequency (/Max) of the processor core. Companies that mass produce high-performance microprocessors commonly have the L1 cache consist of fully-custom macros: to ensure that the performance of the L1 cache does not limit the f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> or throughput of the processor. In addition, it is also common for the custom L1 cache designs to use a two-port 8T or a large 6T bitcell, along with domino read logic and very short BL [2,3]. These designs tradeoff density and area for high performance. This paper presents a different approach, one which can satisfy a range of different applications; a memory compiler that can generate more than 10,000 different high-speed L1 cache macro configurations is proposed. The 7nm L1-cache compiler described in this paper uses a high-current (HC) 6T bitcell, which is more area efficient than an 8T bitcell. The HC bitcell, along with small-signal sensing, allows for long BL (256b), leading to further area efficiency improvements. Since these L1 macros are just as likely to be used in mobile applications as they are to be used in HPC applications, they were implemented using the array dual-rail (ADR) architecture [4]. The ADR architecture (Fig. 11.3.1) allows the periphery circuits of the L1 macro to operate at the same voltage as the processor core: a lower l/ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> results in dynamic power savings. ADR performance is also improved, over an interface dual-rail, when the SRAM and logic supplies are equivalent, as ADR design does not suffer from a level-shifter delays on the inputs or outputs.

Data center (DC) and high performance computing (HPC) applications have traditionally used a combination of copper, multimode fiber and single-mode fiber interconnects with relative percentages that depend on factors such as the line rate, reach and connectivity costs. The balance between these transmission media has increasingly shifted towards optical fiber due to the reach constraints of copper at data rates of 10 Gb/s and higher. The percentage of single-mode fiber deployed in the DC has also grown slightly since 2014, coinciding with the emergence of mega DCs with extended distance needs beyond 100 m. This trend will likely continue in the next few years as DCs expand their capacity from 100G to 400G, increase the physical size of their facilities and begin to utilize silicon-photonics transceiver technology. However there is a still a need for the low-cost and high-density connectivity, and this is sustaining the deployment of multimode fiber for links ≤ 100 m. In this paper, we discuss options for single-mode and multimode fibers in DCs and HPCs and introduce a reduced diameter multimode fiber concept which provides intra-and inter-rack connectivity as well as compatibility with silicon-photonic transceivers operating at 1310 nm. We also discuss the trade-offs between single-mode fiber attributes such as bend-insensitivity, attenuation and mode field diameter and their roles in capacity and connectivity in data centers.

Cloud computing offers new computing paradigms, capacity and flexible solutions to high performance computing (HPC) applications. For example, Hardware as a Service (HaaS) allows users to provide a large number of virtual machines (VMs) for computation-intensive applications using the HaaS model. Due to the large number of VMs and electronic components in HPC system in the cloud, any fault during the execution would result in re-running the applications, which will cost time, money and energy. In this paper we presented a proactive fault tolerance (FT) approach to HPC systems in the cloud to reduce the wall-clock execution time and dollar cost in the presence of faults. We also developed a generic FT algorithm for HPC systems in the cloud. Our algorithm does not rely on a spare node prior to prediction of a failure. We also developed a cost model for executing computation-intensive applications on HPC systems in the cloud. We analysed the dollar cost of provisioning spare nodes and checkpointing FT to assess the value of our approach. Our experimental results obtained from a real cloud execution environment show that the wall-clock execution time and cost of running computation-intensive applications in cloud can be reduced by as much as 30%. The frequency of checkpointing of computation-intensive applications can be reduced up to 50% with our FT approach for HPC in the cloud compared with current FT approaches.

The powerful computing capabilities of supercomputers enable them to execute a wide variety of high performance computing (HPC) applications. However, when executing HPC applications, the low hardware utilization prevents the efficiency of supercomputers from being fully exploited. Performance analysis is an effective way to discover performance bottlenecks. Existing research focuses on the profiling or modeling of HPC application performance, lacking systematic automatic performance analysis and tuning methods. To address the above challenge, in this paper, we propose a composable suite for HPC applications that can achieve low-overhead performance profiling, fine-grained performance modeling and automatic performance tuning. Specifically, a low-overhead profiling method is first proposed to accurately characterize the performance of HPC applications while minimizing the interference of measurement. Then, fine-grained performance models are built to predict the performance of HPC applications based on the profiling sampling. Finally, according to the performance models, an automatic tuning method is designed to improve the performance of coupled HPC applications. The experimental results show that the overhead of our profiling method is less than 15% for the benchmarks and the real-world applications. The average relative error of our modeling method is less than 10%. The optimal layouts contribute to the total running time savings of 16.33% and the total computing fee savings of 31.44%. The effectiveness of our methods is superior to the baselines.

This study evaluates the impact of Artificial Intelligence (AI) applications in power systems on energy security and to determine relevant policy implications. We use a mixed methods approach to analyze the benefits and risks associated with AI implementation on the European power grid, focusing on four key dimensions of energy security: availability, affordability, accessibility, and acceptability. We investigated the benefits of AI using PyPSA, a Python-based model of the European electricity system. Three AI applications were parametrized: load reduction, load shifting, and wind wake steering. We compared scenarios in which these AI applications are widely deployed against a baseline scenario without these applications to determine if AI improves energy security. The study also analyzes risks associated with AI deployment in the power grid. We developed a risk taxonomy centered around six high-level categories: cybersecurity, jurisdictional or sovereignty issues, unexplained or unexpected actions by the model, unethical or illegal decision-making, reliance and trust in decision-making, and supplier dependency and vendor lock-in. Additionally, we conducted a back-casting exercise with subject-matter experts to determine positive and negative future outcomes of AI deployment and identify actions to create positive outcomes and avoid negative ones. The paper presents a set of policy implications for AI on the European synchronous grid. We find that AI applications can improve energy security in power systems. In the scenarios we tested, behind-the-meter applications have a greater impact on energy security than front-of-meter applications. The results suggest that AI applications targeting energy consumption may significantly improve energy security metrics. Keywords: Energy Security, AI, Power Grid, European Electricity System

Artificial Intelligence (AI) was the inspiration that shaped computing as we know it today. In this article, I explore why and how AI would continue to inspire computing and reinvent it when Moore's Law is running out of steam. At the dawn of computing, Alan Turing proposed that instead of comprising many different specific machines, the computing machinery for AI should be a Universal Digital Computer, modeled after human computers, which carry out calculations with pencil on paper. Based on the belief that a digital computer would be significantly faster, more diligent and patient than a human, he anticipated that AI would be advanced as software. In modern terminology, a universal computer would be designed to understand a language known as an Instruction Set Architecture (ISA), and software would be translated into the ISA. Since then, universal computers have become exponentially faster and more energy efficient through Moore's Law, while software has grown more sophisticated. Even though software has not yet made a machine think, it has been changing how we live fundamentally. The computing revolution started when the software was decoupled from the computing machinery. Since the slowdown of Moore's Law in 2005, the universal computer is no longer improving exponentially in terms of speed and energy efficiency. It has to carry ISA legacy, and cannot be aggressively modified to save energy. Turing's proposition of AI as software is challenged, and the temptation of making many domain-specific AI machines emerges. Thanks to Deep Learning, software can stay decoupled from the computing machinery in the language of linear algebra, which it has in common with supercomputing. A new universal computer for AI understands such language natively to then become a Native Supercomputer. AI has been and will still be the inspiration for computing. The quest to make machines think continues amid the slowdown of Moore's Law. AI might not only maximize the remaining benefits of Moore's Law, but also revive Moore's Law beyond current technology.

Significant investments to upgrade and construct large-scale scientific facilities demand commensurate investments in R&D to design algorithms and computing approaches to enable scientific and engineering breakthroughs in the big data era. Innovative Artificial Intelligence (AI) applications have powered transformational solutions for big data challenges in industry and technology that now drive a multi-billion dollar industry, and which play an ever increasing role shaping human social patterns. As AI continues to evolve into a computing paradigm endowed with statistical and mathematical rigor, it has become apparent that single-GPU solutions for training, validation, and testing are no longer sufficient for computational grand challenges brought about by scientific facilities that produce data at a rate and volume that outstrip the computing capabilities of available cyberinfrastructure platforms. This realization has been driving the confluence of AI and high performance computing (HPC) to reduce time-to-insight, and to enable a systematic study of domain-inspired AI architectures and optimization schemes to enable data-driven discovery. In this article we present a summary of recent developments in this field, and describe specific advances that authors in this article are spearheading to accelerate and streamline the use of HPC platforms to design and apply accelerated AI algorithms in academia and industry.

Modern High Performance Computing (HPC) applications, such as Earth science simulations, produce large amounts of data due to the surging of computing power, while big data applications have become more compute-intensive due to increasingly sophisticated analysis algorithms. The needs of both HPC and big data technologies for advanced HPC and big data applications create a demand for integrated system support. In this study, we introduce Scientific Data Processing (SciDP) to support both HPC and big data applications via integrated scientific data processing. SciDP can directly process scientific data stored on a Parallel File System (PFS), which is typically deployed in an HPC environment, in a big data programming environment running atop Hadoop Distributed File System (HDFS). SciDP seamlessly integrates PFS, HDFS, and the widely-used R data analysis system to support highly efficient processing of scientific data. It utilizes the merits of both PFS and HDFS for fast data transfer, overlaps computing with data accessing, and integrates R into the data transfer process. Experimental results show that SciDP accelerates analysis and visualization of a production NASA Center for Climate Simulation (NCCS) climate and weather application by 6x to 8x when compared to existing solutions.

The availability of computing resources has significantly changed due to the growing adoption of the cloud computing paradigm. Aiming at potential advantages such as cost savings through the pay-per-use method and resource allocation in a scalable/elastic way, we witnessed consistent efforts to execute high-performance computing (HPC) applications in the cloud. Performance in this environment depends heavily upon two main system components: processing power and network interconnection. If, on the one hand, allocating more powerful hardware theoretically boosts performance, on the other hand, it increases the allocation cost. In this paper, we evaluated how the network interconnection impacts on performance and cost efficiency. Our experiments were carried out using NAS Parallel Benchmarks and Alya HPC application on Microsoft Azure public cloud provider, with three different cloud instances/network interconnections. The results revealed that through the use of the accelerated networking approach, which allows the instance to have a high-performance interconnect without additional charges, the performance of HPC applications can be significantly improved with a better cost efficiency.

Fault tolerance overhead of high performance computing (HPC) applications is becoming critical to the efficient utilization of HPC systems at large scale. Today's HPC applications typically tolerate fail-stop failures by check pointing. However, check pointing will lose its efficiency when system becoming very large. An alternative method is algorithm-based fault recovery which has been proved to be more efficient than check pointing. In this paper, we first point out by theoretical analysis that algorithm-based fault recovery will also lose its efficiency when systems scale up to Exa flops. Then, a more efficient algorithm-based fault tolerance scheme for HPC applications at large scale is presented. The new method has two novel skills. One is algorithm-based hot replacement, which avoids the stop-and-wait time after failure. Second is background accelerated recovery, which guarantees the system to endure multiple failures in succession. As a case study, this method is incorporated to High Performance Lin pack (HPL). Theoretical analysis shows that the fault tolerance overhead can be reduced to 2/log(p, 2) of that of algorithm-based fault recovery method (p is the number of computation processes), so that the new method will still be efficient in Exascale. Experimental results for up to 1800 processes show that the overhead of the new method is about 25% of that of algorithm-based fault recovery method, which is close to the theoretical prediction.

There is a trend to migrate HPC (High Performance Computing) applications to cloud platforms, such as the Amazon EC2 Cluster Compute Instances (CCIs). While existing research has mainly focused on the performance impact of virtualized environments and interconnect technologies on parallel programs, we suggest that the configurability enabled by clouds is another important dimension to explore.Unlike on traditional HPC platforms, on a cloud-resident virtual cluster it is easy to change the I/O configurations, such as the choice of file systems, the number of I/O nodes, and the types of virtual disks, to fit the I/O requirements of different applications. In this paper, we discuss how cloud platforms can be employed to form customized and balanced I/O subsystems for individual I/O-intensive MPI applications. Through our preliminary evaluation, we demonstrate that different applications will benefit from individually tailored I/O system configurations. For a given I/O-intensive application, different I/O settings may lead to significant overall application performance or cost difference (up to 2.5-fold). Our exploration indicates that customized system configuration for HPC applications in the cloud is important and non-trivial.

The semiconductor industry plays a vital role in driving technological advancements, and the incorporation of AI (Artificial Intelligence) can greatly enhance its efficiency and productivity. Through optimizing material usage and reducing defects, AI can significantly reduce costs and enhance production efficiency and product quality. However, despite the increasing interest in AI applications in the semiconductor industry, comprehensive reviews are lacking to systematically analyze existing research and identify the challenges and opportunities in this field. This review aims to bridge this gap by providing a thorough overview of AI-driven techniques in optimizing semiconductor manufacturing and offering valuable insights for future research directions. The integration of Artificial Intelligence (AI) into chip design marks a transformative phase for the semiconductor industry. Traditional design methodologies, often labor-intensive and time-consuming, are increasingly constrained by human expertise and iterative processes. Generative AI, utilizing advanced machine learning models such as Generative Adversarial Networks (GANs) and Variational Autoencoders (VAEs), offers innovative approaches to automate and optimize various stages of chip design. This paper examines how generative AI can revolutionize chip design by automating complex tasks, including architecture exploration, circuit optimization, and layout generation. Through case studies, we demonstrate significant improvements in design efficiency, performance optimization, and reduced time-to-market. Additionally, we address challenges such as data availability, model interpretability, and the integration of AI-generated designs into existing verification workflows. The findings highlight the potential of generative AI to enhance design capabilities, reduce development costs, and accelerate innovation in semiconductor technology.