Tailoring ATPG for embedded testing

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths.

Digital microfluidic biochips with non-regular arrays are of interest for clinical diagnostic applications in a cost-sensitive market segment. Previous techniques for biochip testing are limited to regular microfluidic arrays. We present an automatic test pattern generation (ATPG) method for non-regular digital microfluidic chips. The ATPG method can generate test patterns to detect catastrophic defects in non-regular arrays where the full reconfigurability of the digital microfluidic platform is not utilized. It automates test-stimulus design and test-resource selection, in order to minimize the test application time. We also present an integer linear programming model for the compaction of test patterns, while maintaining the desired fault coverage. We utilize two fabricated biochips with non-regular microfluidic arrays to evaluate the proposed ATPG method.

During the test mode of flip flop in a chip, a set of input vectors are sent through the flip-flop, it consumes more power consumption than in the normal functional mode. In this paper, we propose a latch with bi -stable element which reduces area as well as the power consumed. The latch proposed consists of simple basic gates involving two inverters back to back which acts as a bi-stable element and a transmission gate with the clock signal used to enable and disable the rest of the circuit with impact on running the latch on Static Timing Analysis. The input test vectors are either given by Automatic Test Pattern Generation (ATPG) or many other methods. We model this using T-Simulation Program with Integrated Circuit Emphasis (T-SPICE) and see the power consumed.

Parallel computing is widely utilized to speed up automatic test pattern generation (ATPG); however, most of today's parallel ATPGs are non-deterministic, which often leads to non-reproducible test pattern sets. This paper presents a fault-parallel test pattern generator: CPP-ATPG; it generates the same test pattern set regardless of the thread count and timing. Besides, it exhibits good speedup scalability as the thread count increases. These are achieved by the circular pipeline processing (CPP) principle, which guides the proposed parallel ATPG to preserve the task processing orders that are necessary to ensure ATPG determinism but with low inter-thread synchronization overhead. Furthermore, a multi-round test generation and compaction strategy is proposed to avoid possible test pattern inflation. Experimental results show that CPP-ATPG exhibits close-to-linear speedup for at least up to 12 threads.

With the advent of the so-called system on a chip, or superchip, telling whether a complex integrated circuit is free of manufacturing flaws has become more difficult than ever before. Few believe that any automatic test equipment (ATE) machine of known architecture will be able to test tomorrow's chips as accurately or as thoroughly as yield and reliability considerations demand. It is for this this reason that different approaches to chip testing such as design for testability (DFT), automatic test pattern generation (ATPG), built-in self-test (BIST) an internal scan design are currently being developed.

DFT (Design for Testability) is a methodology of testing for manufacturing defects in a chip. DFT consists of scan, ATPG (Automatic test pattern generation) methodologies and the BIST (Built in self-test) methods. This paper explores ATPG for pattern generation and LBIST (Logic built-in self-test) for testing. LBIST is explored and tested using pseudorandom test pattern generation. The fault list created for undetected faults are dumped into ATPG and fault specific test patterns are generated. These patterns detect the random pattern resistant faults (which are undetected by pseudorandom testing patterns). Further, a smart compression algorithm is defined to compress the pattern which can be stored inside the chip for LBIST testing, with no added memory overhead, and the minimum extra hardware (which only comprises of combinational logic). The proposed algorithm has been reviewed and analyzed and it has been found that the fault coverage achieved is 86.01%.

The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

This paper describes a mixed-signal IC that employs a test architecture consisting of multiple selectable sub-scan chains (SSCs), which the authors have termed pseudo full scan. This implementation reduces test pattern length and improves fault grading. An additional scan chain of boundary shift register latches (BSRLs) is used to sensitize the analog section of the IC to permit closed-loop testing. A mixed-signal IC using this architecture can be tested with a less expensive digital IC tester. Modeling for standard automatic test pattern generation (ATPG) tools is also presented.

Comet — A new method for the deterministic test pattern generation in c-circuits

The authors present an approach to improve sequential circuit automatic test pattern generation (ATPG) by using E-cells that capture knowledge of circuit functionality without physically modifying the circuit. The approach addresses the problem of test generation for circuits which are inherently testable but outstrip the ATPG algorithm's capacity to generate sufficient fault coverage in reasonable time. Using E-cells the ATPG algorithm processes a less complex virtual circuit. Experimental results on complex industrial designs demonstrate fault coverage improved by 258% and CPU time was reduced by an order of magnitude. >

Due to the continuous shrinking of semiconductor technology, there are more and more subtle errors or faults widely distributed in manufactured chips, and traditional "single" stuck-at fault model may become inappropriate. It is definitely better if all combinations of multiple faults can be completely tested. In this paper, we present ATPG (Automatic Test Pattern Generation) techniques targeting all multiple stuck-at faults, i.e. all combinations of stuck-at faults. That is, given "n" possibly faulty locations in a circuit, the target set of faults consists of 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 fault combinations, as each possibly faulty location is under stuck-at 1, stuck-at 0, or normal/non-faulty. Traditional ATPG flows use fault simulators to eliminate all detectable faults by the current set of test vectors. The problem, however, fault simulators represent fault lists explicitly in the sense that all possible faults are enumerated in the fault lists. This prevents us from dealing with ultra large fault lists, such as 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 faults. We need "implicit" representation of faults in order to deal with such huge numbers of faults or fault combinations. We present SAT based formulations for ATPG of circuits having very large numbers of faults by implicitly eliminating detected faults. We solve a set of SAT problems whose constraints increase pure incrementally (here "pure" means never deleting constraints), and so the entire solving process can be very efficient, as all learnings obtained so far are valid in the following SAT problems. Experiments are performed on combinational parts of ISCAS89 circuits in their AIG (AND-Inverter Graph) representations. We have successfully generated the complete set of test vectors assuming that faults happen only at outputs of gates. Our ATPG techniques can also start with a given set of test vectors. If we start the ATPG processes with a set of test vectors for single stuck-at faults, we can obtain the set of additional test vectors required for multiple stuck-at faults. Results are a little bit surprising in the sense that we need very few additional test vectors for multiple faults, although the numbers of fault combinations are exponentially larger. As far as we know, for the first time, complete test vectors for all stuck-at faults for ISCAS89 circuits where faults happen only at outputs of gates in AIG representations of the circuits have been obtained.

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.

In this paper, we propose a hierarchical automatic test pattern generation (ATPG) framework that can generate custom tests for full-scan systems-on-chip (SOCs) containing intellectual property (IP) cores without revealing much IP. The proposed ATPG is shown to be correct and complete and its average and worst case complexities are shown to be comparable with those of classical ATPG. The proposed ATPG reduces DFT overheads and test application costs. It also enables utilization of a range of test methodologies at the SOC level.

The use of scan test patterns, generated at the gate level with automatic test pattern generation (ATPG) tools in design simulation, was proposed in our previous work to improve verification quality. A drawback of this method is the potential presence of illegal (or unreachable) states (ISEs) causing unwanted behavior and false error detection in the verification process. In this brief, we present a new automated tool that helps overcome this problem. The tool extracts functional constraints at the register transfer level on a VHDL description (it can be easily adapted to any other hardware description language). The constraints extracted are used in the ATPG process to generate pseudofunctional scan test patterns which avoid the ISEs. The whole verification environment incorporating the proposed tool is presented. Experimental results show the tool impact on the reduction of false error detection in verification. In addition, it shows the verification quality improvements with the proposed environment in terms of coverage, time, and complexity.

Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the amount of test escapes compared to conventional automatic test pattern generation (ATPG). Our CAT flow consists of three steps: (1) defect-location identification (DLI), (2) defect characterization based on detailed analog simulation of the cells, and (3) cell-aware automatic test pattern generation (ATPG). This paper focuses on Step 1, as quality and cost are determined by the set of cell-internal defect locations considered in the remainder of the flow. Based on technology inputs from the user and a parasitic extraction (PEX) run that analyzes the cell layouts, we derive a set of open defects on and short defects between both transistor terminals and intra-cell interconnects. The full set of defect locations is stored for later use during failure analysis. Through dedicated DLI algorithms, we identify a compact subset of defect locations for defect characterization and ATPG, in which we include only one representative defect location for each set of equivalent defects locations. For Cadence’s GPDK045 library, the compact subset contains only 2.8% of the full set of defect locations and reduces the time required for defect characterization with the same ratio.