Technology interactions on reticle delivery

This industry faces new challenges every day. It gets tougher as process nodes shrink and the data complexity and volume increase. We are a mask data preparation (MDP) software provider, and have been providing MDP systems to mask shops since 1990. As the industry has, MDP software providers also have been facing new challenges over time, and the challenges get tougher as process nodes shrink and the data complexity and volume increase. We discuss such MDP challenges and solutions in this paper from a MDP software provider’s perspective. The data volume continuously increases, and it is caused by shrinking the process node. In addition, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and inverse lithography technique (ILT) induce data complexity, and it contributes considerably to the increase in data volume. The growth of data volume and complexity brings challenges to MDP system, such as the computing speed, shot count, and mask process correction (MPC). New tools (especially mask writers) also bring new challenges. Variable-shaped E-beam (VSB) mask writers demand fracturing less slivers and lower figure counts for CD accuracy and write time requirements respectively. Now multibeam mask writers are under development and will definitely bring new challenges.

Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of <i>design-aware</i> OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RET) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. Gupta et al. (2003) proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime. We apply a mathematical programming based slack budgeting algorithm to determine edge placement error (EPE) tolerance budgets for all polysilicon gate geometries. These tolerances are then enforced by a commercial OPC tool to achieve up to 24% MEBES data volume and 41% OPC runtime reductions on a suite of six testcases implemented in Artisan TSMC 0.13 /spl mu/m libraries.

With the resolution enhancement techniques such as OPC (Optical Proximity Correction) and SRAF (Sub-Resolution Assist Features), the size of layout data have grown significantly. It is quite common now to find layout files that are tens of GBs in size. Unlike GDSII which can store data hierarchically, mask data formats such as MEBES are essentially flat and more voluminous. Moreover, polygonal data present in layout data files is fractured, thereby increasing the data volume before getting stored in MEBES data format. This results in huge MEBES files. As per the ITRS roadmap of 2005, for a 45nm half-pitch node that is expected to be in use by 2010, the mask data volume for a single layer is expected to reach up to 825 GB. Storing and transferring such large mask data are issues for which the mask industry needs solutions. Historically, MEBES is the most prevalent EB format in the industry. Moreover, in many Mask Data Preparation (MDP) flows, the MEBES format is being used as the de-facto standard for specifying the fractured EB data even though the final target EB machine might be different. In this paper we present techniques for lossless reversible compression of MEBES data, i.e., when the compressed file is decompressed, the generated uncompressed file matches the original MEBES file bit- by-bit. By applying these compression techniques a compression ratio of 5X to 15X can be obtained. In practice, compressing MEBES files is usually a one-time task, but decompression of compressed files is expected to be done multiple times as every time a compressed MEBES file needs processing, it has to be decompressed. MEBES is essentially an efficient data format and the geometries are stored compactly. As a result the compression/decompression techniques described in this paper are quite computation intensive in order to achieve higher compression ratio. This in turn leads to higher CPU time for compression/decompression compared to generic compressors such as gzip. However, as the format-specific compressors produce higher compression ratios, the disk I/O time for compression and decompression is expected to be less compared to the generic compressors such as gzip and gunzip. In spite of this, the format-specific decompressor is usually 3-5X times slower than the generic decompressor such as gunzip. Since decompression is expected to be done more frequently as compared to compression, speeding up decompression is highly desirable. We present a compression technique for MEBES data which enables multiple process threads to decompress the compressed MEBES data. With the multi-core multiprocessor machines becoming quite inexpensive and common, the multi-threaded decompression is expected to perform close to the disk I/O time on such machines. The paper details out the techniques, experimental results in terms of comparative compression ratios, compression and decompression speed using single threads and multiple threads. The possibility of getting higher compression ratios as well as higher or comparable decompression speed makes it more practical to use format specific reversible compression schemes rather than using generic compressors. Even though, the paper focuses on compression and decompression of MEBES, it can be easily extended to the compression of GDSII [1].

A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity and variability. The work described here is motivated by requirements for extreme accuracy and control of variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design of VSB shots and dose assignment.

The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole lithography and double patterning, comparing dimensional control through process window for each OPC method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably manufactured will also be explored.

As the process technology advances to the nanometer nodes, Optical Proximity Correction (OPC) is the most popular Resolution-Enhancement Technique (RET) in industry for subwavelength lithography, and the inter-level dielectric (ILD) thickness variation caused by the planarization step of the Chemical-Mechanical Polishing (CMP) process also plays a key role for interconnect yield. Considering the OPC and CMP effects simultaneously during the routing stage can significantly alleviate the width and thickness variations (and thus the whole 3D geometry variations) of post-layout RET and CMP operations. In this paper, we first present an efficient, yet sufficiently accurate closed-form formula for printed width computation and dummy-insertion-aware routing cost derivation. The formula provides a cost modeling for post-layout OPC and CMP optimization during routing. Incorporating the OPC and CMP costs, the router can be guided to optimize the effects of layout correction and planarization. Compared with the state-of-the-art OPC-friendly router, QL-MGR (which does not consider CMP), the experimental results show that our approach can achieve respective 19% and 6% reductions in the maximum and average layout distortions. Compared with the state-of-the-art CMP-aware router, TTR (which does not consider OPC), the experimental results show that our approach can achieve respective 19% and 25% reductions in the peak-to-peak thickness and thickness variance. These results indicate that our simultaneous OPC- and CMP-aware router contributes a significant improvement for layout integrity.

Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.

Sub-Resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the Optical Proximity Correction (OPC) stage. The main features and the SRAFs are optimized to account for their edge placement and process window metrics respectively. The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.

With the dramatically increase of design complexity and the advance of semiconductor technology nodes, huge difficulties appear during design for manufacturability with existing lithography solutions. Sub-resolution assist feature (SRAF) insertion and optical proximity correction (OPC) are both inevitable resolution enhancement techniques (RET) to maximize process window and ensure feature printability. Conventional model-based SRAF insertion and OPC methods are widely applied in industrial application but suffer from the extremely long runtime due to iterative optimization process. In this paper, we propose the first work developing a deep learning framework to simultaneously perform SRAF insertion and edge-based OPC. In addition, to make the optimized masks more reliable and convincing for industrial application, we employ a commercial lithography simulation tool to consider the quality of wafer image with various lithographic metrics. The effectiveness and efficiency of the proposed framework are demonstrated in experimental results, which also show the success of machine learning-based lithography optimization techniques for the current complex and large-scale circuit layouts.

The feasibility of Hot Spot Fixing (HSF) system in DfM flow is studied and reported. Hot spot fixing using process simulation is indispensable under low-k1 lithography process for logic devices with advanced design rule (DR). Hot spot such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Proper calibration of DR, mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with most careful calibration of every process, unexpected potential hot spots are occasionally left in the design layout 1-2. OPC optimization is useful for maximizing common process margin, but it cannot expand individual pattern's process margin without modification of design layout. So, at an early design stage, hot spot extraction using lithography compliance check (LCC) and manual modification of design at hot spots will be a simple and useful method. The problem is that, it is difficult to determine how to modify layout in order to be consistent with DR, MDP/OPC rule. For proper layout modification, intimate knowledge of the entire process would be necessary, and moreover, the modification work often tends to be iterative, and thus time-consuming. Therefore, using our automated HSF system in the cell design stage and also the chip design stage is helpful for fixing design layout while avoiding fatal hot spot occurrence, with enough process margin and also with short turnaround time (TAT) 3-4. The basic system flow in the developed system is as follows; LCC extracts potential hot spots, and the hot spots are categorized by lithography error mode, grade, and surrounding context. And then, hot spot modification instructor, taking the surrounding situation into consideration, generates modification guide for every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. The design modification process is verified with design-rule checker (DRC) and process simulation to confirm hot spot elimination without side effect. In this work, HSF is implemented in the design flow for various logic devices of 65 nm node. We extend modification target layers to multiple critical layers, including active area, poly, local metal wire and intermediate metal wire. The feasibility of the provided HSF system has been studied by applying it to around one hundred data of various sizes with respect to pattern fixing rate and turn around time (TAT). Moreover, process margin expansion including depth of focus (DOF) and exposure latitude (EL), in small layout was verified using process simulation and also by experimental results, namely, scanning electron microscope (SEM) images of focus exposure matrix. The detailed results are shown in the paper.

Over the years process development engineers found creative ways to extent the capabilities of existing imaging techniques to enable production of the next technology node. For the 45nm node the immersion technology is being prepared for production, along with other resolutions enhancement techniques such as illuminator polarization. In parallel with the development of these tools, modeling techniques are being developed, which are needed in order to establish the design flows and to set up the Optical Proximity Correction (OPC) and mask data preparation. There is a clear need to validate these models and verify them in an early stage. With the equipment not being available yet, other methods like Maxwell simulators and special test equipment are used for such validations. In this paper initial model verification and validation work is presented of a hyper NA models developed for the 45nm technology node. Models with different illuminator settings are used and compared with Maxwell simulators and experimental measurements obtained with an Exitech MS-193i immersion micro-exposure tool.

Optical proximity correction (OPC) methods are resolution enhancement techniques (RET) used extensively in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. Recently, a set of generalized gradient-based OPC optimization methods have been developed to solve for the inverse lithography problem under coherent illumination. Most practical lithography systems, however, operate under partially coherent illumination due to non-zero width sources and off-axis illumination from spatially extended sources. OPC methods derived under the coherent illumination assumption fail to account for the nonlinearities of partially coherent illumination and thus perform poorly in the latter scenario. This paper focuses on developing gradient-based binary mask optimization methods which account for the inherent nonlinearities of partially coherent systems. Two nonlinear models are used in the optimization. The first relies on a Fourier representation of the nonlinear model which approximates the partially coherent system as a sum of coherent systems. The second model is based on an average coherent approximation which is computationally faster. In order to influence the solution patterns to have more desirable manufacturability properties, wavelet regularization is added to the optimization framework. The advantages and limitations of both models in the inverse lithography problem are discussed and several illustrative simulations are presented.

As the feature size of advanced integrated circuits keeps shrinking, resolution enhancement technique (RET) is utilized to improve the printability in the lithography process. Optical proximity correction (OPC) is one of the most widely used RETs aiming at compensating the mask to generate a more precise wafer image. In this paper, we put forward a level-set based OPC with high mask optimization quality and fast convergence. In order to suppress the disturbance of the condition fluctuation in lithography process, we propose a new process window-aware cost function. Then, a novel momentum-based evolution technique is adopted, which demonstrates substantial improvement. Moreover, graphics processing unit (GPU) is leveraged for accelerating the proposed algorithm. Experimental results on ICCAD 2013 benchmarks show that our algorithm outperforms all previous OPC algorithms in terms of both solution quality and runtime overhead.

The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography [4]. However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.