Test pattern extraction for lithography modeling under design rule revisions

Techniques for SAT-based constrained test pattern generation

Manufacturing has been incapable of keeping up with Moore's law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.

Parallel computing is widely utilized to speed up automatic test pattern generation (ATPG); however, most of today's parallel ATPGs are non-deterministic, which often leads to non-reproducible test pattern sets. This paper presents a fault-parallel test pattern generator: CPP-ATPG; it generates the same test pattern set regardless of the thread count and timing. Besides, it exhibits good speedup scalability as the thread count increases. These are achieved by the circular pipeline processing (CPP) principle, which guides the proposed parallel ATPG to preserve the task processing orders that are necessary to ensure ATPG determinism but with low inter-thread synchronization overhead. Furthermore, a multi-round test generation and compaction strategy is proposed to avoid possible test pattern inflation. Experimental results show that CPP-ATPG exhibits close-to-linear speedup for at least up to 12 threads.

In this paper, we propose a novel test architecture called the pseudo-full scan (PFS) architecture to reduce test application time and power consumption simultaneously. We also present a test generation procedure to generate a set of test patterns that is suitable for the PFS architecture. The method reduces test application time and power consumption by (1) scanning only a fraction of the flip-flops, and (2) compressing the test vector sequence into a much shorter one. Experimental results show that our method has the advantages of reducing the test application time and power dissipation compared to the conventional scan methodology.

At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the manufacturability of their layouts because of the lack of understanding of the litho process. Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models. Direct validation of AF rules is required at development phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically optimize performance of recipe bearing all these variables in mind. In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for contact coverage, etc. Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly used method of least intensity variation.

Adaptive path-delay testing is a testing methodology that reduces redundant test patterns based on the measured process condition of a die under test (DUT). To improve testing efficiency, process conditions are clustered into a limited number of clusters, each of which has a corresponding set of test patterns. The test pattern set of a cluster must include all potential timing-critical paths of all process conditions in the cluster. Hence, high-quality clustering is needed to minimize redundant test paths. In this paper, we propose a new clustering heuristic to minimize the expected number of redundant test paths in adaptive path-delay testing. Our experimental results on randomly generated testcases show that the proposed clustering heuristic can reduce the expected number of test paths by up to 40% compared to the previous Greedy clustering algorithm of Uezono et al. [5]. To address unique attributes of an industrial testcase obtained from the authors of [5], we integrate the dynamic-programming restricted-partitioning technique of [1], which improves the expected number of test paths by up to 5% compared to the Greedy algorithm.

A layout design that passes the design rule check (DRC) may still have manufacturing problems today, especially around areas of critical patterns. Thus a design-for-manufacturability (DfM) model, which can simulate the process from designed layout to wafer and predict the final contours, is necessary. A new kind of DfM model called free-elementmodel (FEM) is proposed in this paper. The framework of FEM is borrowed from the forward process model, which is basically a set of convolution kernels in matrix form, yet the unknown variables are the kernel elements instead of process parameters. The modeling process is transformed into a non-linear optimization problem, with equality constraints which involve norm-2 regulation of kernels and inner production of any two kernels to keep the normalization and orthogonality of optimized kernels. Gradient-based method with Lagrange penalty function is explored to solve the optimization problem to minimize the difference between simulated contours and real contours. The dimension of kernels in FEM is determined by the cutoff frequency and the ambit. Since kernels are calculated by optimization method instead of decomposition of transmission cross coefficient (TCC), every element of kernels becomes a factor to describe the process. FEM is more flexible, and in it all effects that can be integrated into convolution kernels join naturally, such as the resist deviation and asymmetry of the process. No confidential process parameters, for example NA and defocus, appear in FEM explicitly, and thus the encapsulated FEM is suitable for IC manufacturers to publish. Moreover, enhancements and supplements to FEM are discussed in this paper, including the sufficiency of test patterns. In our experiments, DfM models for 2 process lines are generated based on test patterns, and the results show that the simulated shapes have an area error less than 2% compared to the real shapes of test patterns and an area error less than 3% compared to the shapes in typical blocks chosen from chip for verification purpose. The root mean square error of contour deviation between the 2 simulation results from FEM and conventional lithographic model is 10nm in a 65nm process.

After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis.

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

The threat of hardware Trojans has been widely recognized by academia, industry, and government agencies. A Trojan can compromise security of a system in spite of cryptographic protection. The damage caused by a Trojan may not be limited to a business or reputation, but could have a severe impact on public safety, national economy, or national security. An extremely stealthy way of implementing hardware Trojans has been presented by Becker et al. at CHES'2012. Their work have shown that it is possible to inject a Trojan in a random number generator compliant with FIPS 140-2 and NIST SP800-90 standards by exploiting non-zero aliasing probability of Logic Built-In-Self-Test (LBIST). In this paper, we present two methods for modifying LBIST to prevent such an attack. The first method makes test patterns dependent on a configurable key which is programed into a chip after the manufacturing stage. The second method uses a remote test management system which can execute LBIST using a different set of test patterns at each test cycle.

Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.

This paper proposes a low power efficient Built in Self Test (BIST) with Test Pattern Generation (TPG) technique, which reduces power dissipation during testing. In general, the correlations between the consecutive test patterns are higher during normal mode than during testing mode. The proposed approach uses the concept of reducing the transitions in the test patterns generated by conventional Linear Feedback Shift Register (LFSR) . The transitions are reduced by increasing the correlation between the successive bits in the test pattern, which is done with the help of modified LFSR. This approach eliminates the need for an external tester. The simulation result shows that the power dissipated during testing is reduced in modified LFSR than in conventional LFSR.

The test pattern generator (TPG) in deterministic BIST often suffers from some problems such as extra test power consumption, area overhead and idle test cycles. In this paper, an efficient algorithm is proposed to synthesize a built-in TPG from low power deterministic test patterns without inserting any redundancy test vectors. The structure of TPG is based on the non-uniform cellular automata (CA) and is used to test combinational circuits. And the algorithm is based on the nearest neighborhood model, which can find an optimal non-uniform CA topology to generate given low power test patterns. Simulation results using benchmark combinational circuits show that the generator is efficient to generate the deterministic test patterns in terms of power consumption, area overhead and test time.

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths.