Test pattern generation and clock disabling for test time and power reduction

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time comparedto the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time.

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan. >

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

Techniques for SAT-based constrained test pattern generation

While technology is being developed, design rules undergo a number of revisions. An initial lithography model built with test patterns before the revisions inherently become inaccurate for the revised patterns. Preparing a new test layout and updating a lithography model every time design rules are revised is not practical, and cannot be a solution. We prepare some synthetic patterns in addition to initial test patterns. Synthetic patterns originate from popular test pattern generator (TPG), while projected design rule changes are taken into account. A challenge is to sort out the synthetic patterns which are really necessary in building a generic lithography model when they are used together with test patterns. Each pattern, either synthetic or test, is identified in image parameter set (IPS) space. For each test pattern in IPS space, two concentric spheres are drawn; outer one indicating the region where revised versions of test pattern may exist, and inner one indicating the region which is well covered by test pattern alone. Synthetic patterns that reside in the region bounded by the two spheres are kept, while the others are dropped. Clustering is now performed on test patterns and synthetic patterns separately, and representative pattern is drawn from each cluster. When a set of representative patterns are used to build a lithography model in 10nm memory devices, it achieves 43.5% lower CD root mean square error (RMSE) for revised design layout compared with only using a set of initial test patterns.

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

Parallel computing is widely utilized to speed up automatic test pattern generation (ATPG); however, most of today's parallel ATPGs are non-deterministic, which often leads to non-reproducible test pattern sets. This paper presents a fault-parallel test pattern generator: CPP-ATPG; it generates the same test pattern set regardless of the thread count and timing. Besides, it exhibits good speedup scalability as the thread count increases. These are achieved by the circular pipeline processing (CPP) principle, which guides the proposed parallel ATPG to preserve the task processing orders that are necessary to ensure ATPG determinism but with low inter-thread synchronization overhead. Furthermore, a multi-round test generation and compaction strategy is proposed to avoid possible test pattern inflation. Experimental results show that CPP-ATPG exhibits close-to-linear speedup for at least up to 12 threads.

Single input change (SIC) sequence for VLSI testing has been researched because of effectiveness to more test fault models and low power consumption testing. It is the high fault coverage in deterministic built-in self-test (BIST) with low test cost and short test application time. The sequential single input change (SSIC) sequence used in deterministic BIST is presented in this paper for decreasing the dynamic power, reducing test application time and increasing fault coverage. The selection of seed vectors is the significant technique in deterministic BIST. The critical features of SSIC sequence are proposed for selecting seed vectors. The SSIC sequence generator is designed. The simulation results using benchmark circuits show that the SSIC sequences can increase fault coverage and decrease application time than random SIC sequences. SSIC sequence also has low dynamic power consumption.

Available register-transfer level (RTL) test generation techniques do not make a concerted effort to reduce the test application time associated with the derived tests. Chip tester memory limitations, increasing tester costs, etc., make it imperative that the issue of generating compact tests at the RTL be addressed and consolidated with the known gains of high-level testing. In this paper, the authors provide a comprehensive framework for generating compact tests for an RTL circuit. They develop a series of techniques that exploit the inherent parallelism available in symbolic test(s) derived for RTL module(s). These techniques enable them to schedule testing of multiple modules in parallel as well as perform test pipelining. In addition, the authors also present design for testability (DFT) techniques for lowering test application time. Using a maximum bipartite matching formulation, they choose a low-overhead set of test enhancements that can achieve compact tests. The authors' techniques can seamlessly plug into any generic high-level test framework. Their experimental results in the context of one such framework indicate that the proposed methodology achieves an average reduction in test application time of 54.2% for the example circuits.

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

Single input change (SIC) test sequence has been investigated in recent years because it is effective to reduce the test power consumption. Deterministic built-in self-test (BIST) can achieve the high fault coverage with relatively short test application time and low test cost. In this paper, seeds selection scheme of SIC sequences based on deterministic ATPG test patterns is proposed for decreasing the test power consumption and test application time with high test fault coverage. Proper selection of SIC seeds is the key aspect to a successful low power deterministic BIST technique. Furthermore, simulated annealing algorithm is used to optimize the numbers of seeds. A simple hardware structure can implement the generation of SIC sequences. Experimental results based on ISCAS'85 benchmark circuits demonstrate that the proposed algorithm can reduce the number of SIC seeds. Test application time and average power can be decreased, and test fault coverage also keep high compared to random SIC (RSIC) test sequences.

The test pattern generator (TPG) in deterministic BIST often suffers from some problems such as extra test power consumption, area overhead and idle test cycles. In this paper, an efficient algorithm is proposed to synthesize a built-in TPG from low power deterministic test patterns without inserting any redundancy test vectors. The structure of TPG is based on the non-uniform cellular automata (CA) and is used to test combinational circuits. And the algorithm is based on the nearest neighborhood model, which can find an optimal non-uniform CA topology to generate given low power test patterns. Simulation results using benchmark combinational circuits show that the generator is efficient to generate the deterministic test patterns in terms of power consumption, area overhead and test time.

Dynamic power dissipation during scan-based testing of a CMOS digital circuit is reported to be a major issue of concern. The three main components of test power in scan based designs are the logic power, the sequential power and the clock power. This paper presents Integrated Scan cell and Test Vector reordering schemes for linear and non-linear (Double Tree) scan chains, with an objective to reduce the sequential test power. In this regard, it makes two important contributions: (a) It improves the scan cell reordering (SCR) algorithm proposed in Ref. [1] for the linear scan architecture. It then integrates this improved SCR algorithm with a Test Vector Reordering (TVR) strategy that results in further reduction of the sequential test power. (b) It proposes and evaluates scan cell and test vector reordering strategies for the double tree scan (DTS) architecture. It is also observed that for some classes of circuits the TVR provides more reduction of sequential test power than the SCR. Applying the proposed techniques on ISCAS benchmark circuits results in significant sequential test power reduction (with a maximum of 30% and 29.16% for linear and double tree scan architectures respectively) when compared to that output by a commercial tool.

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG