Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Scan architectures represent the most used approach for testing digital integrated circuits. While several methods have been proposed for reducing the power dissipation due to scan shifting, very little work has been done towards reducing the power dissipation during the capture cycles. This paper proposes a method of transforming a typical scan architecture for reducing the power dissipation during both the shifting cycle and the capture cycle. The basic idea is to split the the scan chain into multiple length-balanced partitions and to enable only one partition at each test clock. This way, instead of having all the scan cells active at the same time, only a fraction of them will be active in each test clock cycle, which will reduce substantially the power dissipation in the circuit under test. Unlike previously proposed methods for shifting power reduction based on scan chain partitioning which use a single capture clock per test cycle, our approach uses multiple capture clocks per test cycle, which allows enabling only a fraction of the scan chain during each shift or capture clock, thus reducing the switching activity in the circuit under test not only during shifting but also during capture. Therefore, the proposed method represents an unified solution for reducing both shifting and capture power dissipation during scan-based test. The proposed method also allows full reuse of the test vectors of the original scan architecture.

Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for current research. Scan chain reordering is widely used method to reduce test power. In this paper, a Hamming distance based distributed reordering for loading and unloading scan chain vector is proposed. This method focuses on how and where weighted transitions occur. In current scenario of VLSI the manufacturing cost and area of transistor is no longer a big issue for current VLSI world. In this context, the proposed method shows promising results in reduction of test power at a cost of area. The experimental results for widely sited ISCAS'89 benchmark circuits are presented to show the effectiveness of the proposed scheme.

This tutorial discusses the most important and practical DFT technique in industry — scan in detail: scan cells, scan chains, scan I/O, scan architectures, scan protocols, scan rules, scan timing, scan power, scan debug; overview of JTAG and BIST. It also covers at-speed scan testing and statistical timing scan testing as well as recent advances in DFT including IJTAG and IEEE P1149.7.

Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process.

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length.

In this paper, we propose a novel test architecture called the pseudo-full scan (PFS) architecture to reduce test application time and power consumption simultaneously. We also present a test generation procedure to generate a set of test patterns that is suitable for the PFS architecture. The method reduces test application time and power consumption by (1) scanning only a fraction of the flip-flops, and (2) compressing the test vector sequence into a much shorter one. Experimental results show that our method has the advantages of reducing the test application time and power dissipation compared to the conventional scan methodology.

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

Scan testing is one of the Design for Testability (DFT) techniques that is widely being used to detect the emerging manufacturing defects in nanometer process technology. However, due to the advancement in System-on-Chip (SoC), over hundred million of logic gates have been implemented in a design resulting in high power dissipation and it has been revealed that power dissipation during scan testing could achieve three times higher than during normal operation due to the switching activity. Thus, the aim of this paper is to investigate the number of scan chains and Automatic Test Pattern Generation (ATPG) X-filling method in reducing the switching power and switching activity. In this work, 12 ISCAS89 benchmark circuits are used to run the scan test by using DFT Compiler and TetraMAX ATPG from Synopsys. Single scan chain up to 20 scan chains is implemented during scan chain insertion and 4 distinct ATPG X-filling methods—random filling, 0-filling, 1-filling and adjacent filling is applied. The switching power and switching activity for each iteration is evaluated to find the optimum number of scan chains and the best ATPG X-filling for each circuit. The simulation results show that out of 12 circuits, 5 of them exhibit preference towards single-digit number of scan chains to achieve optimal switching power performance and the decrement of switching power is ranged from 0.06% to 7.18% compared to single scan chain. Meanwhile, 7 out of 12 circuits gravitate towards 0-filling in reducing switching activity. The decrement of switching activity ranged from 4.23% to 60.63%.

Shrinking power budgets in low power system-on-chips (SoCs) have elevated test power consumption as a major consideration for chip design and test engineering teams. Many traditional automatic test pattern generation (ATPG) and design-for-test (DFT) techniques for test power reduction are either effective for circuits not using test data compression hardware or have implications on the physical design cycle. This paper describes a technique for reducing peak current during scan based testing that can work in the presence of compression, and impose no restrictions on physical design, e.g. related to chip clocking. We propose low-design effort modifications to the test compression logic (wrapper-like changes) that enable us to (a) bypass scan chains or groups of them and (b) shift in constant values into the bypassed flip-flops for lowering the instantaneous current drawn. The modifications are easily localized to a scan chain wrapper that can be used with any scan compression solution. An SoC using low-power scan chain wrappers provides sufficient configurability (scan chains bypassed or scan chains included) to explore different power reductions with test cost trade-offs. We describe a methodology that allows us to manage the inherent configurability available in our solution. For empirical validation, we have implemented low-power scan chain wrappers for a subset of scan chains in a recently taped-out 65nm low-power SoC. We present experimental data from ATPG and initial silicon power measurements for this chip to demonstrate the benefits and limitations of the proposal.

Power consumption during scan-based testing can be higher than that of normal mode opeartions, which can cause yield loss and degradation of reliability. This paper proposes a scan cell reordering algorithm to reduce the test power consumption during scan-based testing. The proposed algorithm considers both shift-out operations and shift-in operations. A cumulative weighted transition (CWT) is proposed and compared to minimize the test power consumption. Experimental results show that the porposed method greatly reduces the average power during scan testing.

The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

The random-like filling strategy pursuing high compression for scan test introduces large test power. To pursue high compression in conjunction with reducing test power for multiple scan chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple scan designs. The scheme utilizes a buffer, which supports fast load using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied ATPG-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with little area design overhead

Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem; and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger ISCAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.