Test set size minimization and fault detection effectiveness: A case study in a space application

Random pattern fault simulation is known to be an efficient method for accelerating test generation process but it is not suited for generating compact test sets because a test set generated by random pattern fault simulation contains many redundant test vectors. In this paper through a set of experiments we first demonstrate the inverse influence of the initial test set size on the final test set size obtained after compaction. We then propose a novel method of deriving compact test sets based on the random pattern fault simulation and compact test generation already proposed. Experimental results show that for the benchmark circuits our method produces minimum or near minimum test sets in substantially less run time than the methods that do not make use of random vectors.

An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with n drops below a certain level. We introduce three parameters of an n-detection test set to measure saturation of the test generation process: (1) the fraction of faults detected n times or less by the test set, (2) the fraction of faults detected fewer than n times by the test set, and (3) the test set size relative to the size of a one-detection test set. We demonstrate that the behavior of each one of these parameters follows a unique pattern as n is increased, and certain features of this behavior can be used to identify saturation. All the parameters are easy to compute during the test generation process.

Software testing is a critical part of software development. As new test cases are generated over time due to software modifications, test suite sizes may grow significantly. Because of time and resource constraints for testing, test suite minimization techniques are needed to remove those test cases from a suite that, due to code modifications over time, have become redundant with respect to the coverage of testing requirements for which they were generated. Prior work has shown that test suite minimization with respect to a given testing criterion can significantly diminish the fault detection effectiveness (FDE) of suites. We present a new approach for test suite reduction that attempts to use additional coverage information of test cases to selectively keep some additional test cases in the reduced suites that are redundant with respect to the testing criteria used for suite minimization, with the goal of improving the FDE retention of the reduced suites. We implemented our approach by modifying an existing heuristic for test suite minimization. Our experiments show that our approach can significantly improve the FDE of reduced test suites without severely affecting the extent of suite size reduction

The problem of computing the minimum size of a test set for a combinational circuit is considered. It is known that the minimum test set size of a combinational circuit can be determined in polynomial time for fanout free circuits, while even for circuits with non-reconvergent fanout, the minimum test set size problem is NP-Hard. We extend the class of circuits for which a minimum test set can be constructed in polynomial time to include a class of circuits with fanout, called restricted fanout circuits. Restricted fanout circuits are characterized using an undirected graph describing the structure of the circuit. The graph for these circuits must be free of (undirected) cycles. In addition, the paper demonstrates a novel application of dynamic programming to test generation problems.

Test case prioritization is used in regression testing to schedule the execution order of test cases so as to expose faults earlier in testing. Over the past few years, many test case prioritization techniques have been proposed in the literature. Most of these techniques require data on dynamic execution in the form of code coverage information for test cases. However, the collection of dynamic code coverage information on test cases has several associated drawbacks including cost increases and reduction in prioritization precision. In this paper, we propose an approach to prioritizing test cases in the absence of coverage information that operates on Java programs tested under the JUnit framework-an increasingly popular class of systems. Our approach, JUnit test case Prioritization Techniques operating in the Absence of coverage information (JUPTA), analyzes the static call graphs of JUnit test cases and the program under test to estimate the ability of each test case to achieve code coverage, and then schedules the order of these test cases based on those estimates. To evaluate the effectiveness of JUPTA, we conducted an empirical study on 19 versions of four Java programs ranging from 2K-80K lines of code, and compared several variants of JUPTA with three control techniques, and several other existing dynamic coverage-based test case prioritization techniques, assessing the abilities of the techniques to increase the rate of fault detection of test suites. Our results show that the test suites constructed by JUPTA are more effective than those in random and untreated test orders in terms of fault-detection effectiveness. Although the test suites constructed by dynamic coverage-based techniques retain fault-detection effectiveness advantages, the fault-detection effectiveness of the test suites constructed by JUPTA is close to that of the test suites constructed by those techniques, and the fault-detection effectiveness of the test suites constructed by some of JUPTA's variants is better than that of the test suites constructed by several of those techniques.

<p>Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.</p> <p>At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.</p> <p>We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.</p> <p>In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced</p> <p>by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.</p>

This study examines the implementation of Test Case Prioritization (TCP) using the Greedy Algorithm (GA) to enhance regression testing efficiency within a financial technology company's software development cycle. With testing durations increasing significantly, this study aims to address inefficiencies by applying the Greedy Algorithm to optimize test suite size and fault detection. The research methodology involves applying the Greedy Algorithm during the Regression Testing phase, comparing the prioritized suite with the original suite using metrics such as Average Percentage Fault Detection (APFD) and Test Suite Size Reduction (TSSR). Results show that the Greedy Algorithm achieved substantial improvements in both test suite size and fault detection effectiveness across different projects. For Project A, the test suite was reduced from 51-22 test cases, achieving a TSSR of 56.8%, with an APFD increase of 206.21%, rising from 0.0853-0.2613. Project B demonstrated even greater optimization, reducing the test suite from 36-8 test cases, resulting in a TSSR of 77.8% and an APFD improvement of 83.92%, rising from 0.3194-0.5875. These outcomes underscore the algorithm’s effectiveness in eliminating redundant test cases, accelerating testing, and enhancing fault detection thereby supporting the company's goal of faster release cycles without compromising quality.

This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit. We also show non-trivial lower bounds for the size of a minimum complete test set.

SummaryAccurate prediction of the solubility of chemical substances in solvents remains a challenge. The sparsity of high-quality solubility data is recognized as the biggest hurdle in the development of robust data-driven methods for practical use. Nonetheless, the effects of the quality and quantity of data on aqueous solubility predictions have not yet been scrutinized. In this study, the roles of the size and the quality of data sets on the performances of the solubility prediction models are unraveled, and the concepts of actual and observed performances are introduced. In an effort to curtail the gap between actual and observed performances, a quality-oriented data selection method, which evaluates the quality of data and extracts the most accurate part of it through statistical validation, is designed. Applying this method on the largest publicly available solubility database and using a consensus machine learning approach, a top-performing solubility prediction model is achieved.

This paper deals with two important related problems in the area of detection of single faults in combinational logic networks. The first is to determine the different equivalence classes of all possible single faults in the given network and this has been achieved by introducing the concept of a new typo of fault graph. Algorithms have been developed to construct the fault graph of a given combinational network from the fault graphs of the component gates and to enumerate the equivalence classes of faults from the fault graph of the network. The second problem, dealt with in this paper, is to enumerate the minimal complete test set to detect single faults in the network and this has been carried out by utilizing the concept of boolean difference in a new manner, so that the computational complexity has been greatly reduced compared to the existing procedures of fault detection by boolean difference

In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and IDDQ testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and IDDQ test. Also, the results of IDDQ based test sets (vectors generated specifically for IDDQ testing) are compared with that of stuck-at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridging faults in IDDQ testing.

Programmable array logic (PAL) devices can be used for realising both combinational and sequential circuits. The final behaviour of a PAL chip is determined by the fuse pattern in this chip. The paper presents a systematic procedure for generating a minimal test set to examine whether a programmed chip functions as expected. The upper bound of the size of a test set generated by the proposed procedure is also derived. >

SpinePose was developed in 2024 as a novel artificial intelligence (AI) tool to automatically predict spinopelvic parameters with high accuracy and without the need for manual entry. The authors' published results demonstrated excellent performance comparable to a fellowship-trained spine surgeon with more than 15 years of experience. To date, there have not been any studies that have externally validated the performance of AI-based spinopelvic parameter measurement tools on data acquired from other institutions. To assess the generalizability of SpinePose, the authors report its performance on an external set of heterogeneous whole-spine scoliosis radiographs obtained from an outside institution. SpinePose was trained/validated on a dataset of 761 sagittal whole-spine scoliosis radiographs from a single institution, with expert-level performance on both whole-spine and lumbosacral radiographs. In this study, the existing SpinePose model was used for inference on a new set of 49 whole-spine radiographs acquired at a tertiary academic hospital located out of state. Externally acquired radiographs represented a diverse set of images, incorporating patients who had undergone instrumentation and those who had not, and a wide variety of fusion constructs including complex deformity patients. Predicted measures included sagittal vertical axis (SVA), pelvic tilt (PT), pelvic incidence (PI), lumbar lordosis (LL), and T1-pelvic angle (T1PA). Predicted parameter values relative to ground-truth manual annotations were calculated to determine the model's accuracy. Of the 49 images, 35 (71.4%) had instrumentation compared with 51.0% and 57.5% in the original SpinePose training and testing sets, respectively. All 5 parameters in the external dataset were significantly different at baseline compared with the original test set (p < 0.01). SpinePose accurately predicted all 5 spinopelvic parameters without any statistically significant differences: SVA, 50.7 mm vs 52.3 mm (p = 0.85); PT, 27.6° vs 30.5° (p = 0.24); PI, 58.0° vs 61.8° (p = 0.17); LL, 40.4° vs 42.4° (p = 0.77); and T1PA, 24.8° vs 28.0° (p = 0.21) when comparing ground truth annotations with predicted values. SpinePose was able to accurately predict spinopelvic parameters on an external validation cohort that was generated independently from the images on which the model was trained and validated. This highlights the generalizability of SpinePose to be implemented on novel images from other institutions and geographic settings with high accuracy and minimal preprocessing. The implementation of AI tools more broadly will help standardize our ability to both deliver and provide spine care and assist with surgical treatment and management of spine patients.

The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.

Health monitoring and fault detection are becoming more and more important in electrical machine systems due to the increasing demand for reliability. Winding turn fault is a common fault in permanent magnet (PM) machines, which can cause severe damages and requires prompt detection and mitigation. High resistance connection fault, which results in phase asymmetry may also occur but does not require immediate shutdown. Thus, apart from the fault detection, the classification between the two faults is also required. In this paper, a new technique for detecting and classifying turn fault and HRC fault by utilizing both the high and low frequency components of the zero sequence voltage is proposed with the enhanced sensitivity. The dependence on the operating conditions is minimized with the proposed fault indicators. The effectiveness of fault detection and classification has been verified by extensive experimental tests on a triple redundant fault tolerant PM assisted synchronous reluctance machine. The robustness of the turn fault detection in transient states and under no load conditions has also been demonstrated.