Systematic procedure for test generation of PAL-based circuits

A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation. >

Chapter 10 - Programmable Logic Devices

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.

Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can’t be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

Programmable logic arrays (PLA) are highly regular circuits which compute suitable Boolean functions. PLAs are a popular circuit design especially in microcontrollers. PLA folding is a technique for minimizing the area of such PLA. Folding can be formulated in purely graph-theoretic terms. In this paper, we study PLA for a very special class of Boolean functions, namely indicator functions of intervals of binary numbers. As a possible application, we can imagine PLA which shall supervise that an input value lies in a prescribed tolerance interval. From a mathematical point of view, the connection of these interval indicator functions with threshold graphs and cographs is interesting. Our study naturally leads to the folding problem in cographs which is shown to be solvable in linear time. In sections 1-2 we introduce the basic notions. In section 3 we prove a theorem on minimal normal forms of interval indicator functions, thereby motivating the folding problem on cographs. A linear time algorithm solving this problem is derived in section 4. Finally, in section 5, we mention some related results and possible directions of further research.

Logic synthesis for PAL-based CPLD-s based on two-stage decomposition

<p>Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.</p> <p>At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.</p> <p>We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.</p> <p>In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced</p> <p>by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.</p>

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure.

The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.

Programmable Logic Arrays (PLA) are finding increasing use as a cost-effective means to utilize LSI electronics. In this paper, three classes of faults, namely stuck faults, shorts and cross-point defects are defined and characterized in a PLA. The relationship between the test sets and their faults among all three classes are discussed. Finally, an algorithm for generating a test set for all three classes of faults is presented.

Digital Systems Design with FPGAs and CPLDs

A decomposition of a programmable logic array (PLA) into two cascaded PLAs is considered. The problem is divided into two subproblems: a partition problem, which finds the partition of the input variables, and an encoding problem, which finds an encoding of signals between two PLAs. Multiple-valued decomposition theory is used to find a good partition of the input variables. Experimental results show that serial decomposition reduces the total PLA size by 10% to 30%. >

Very large scale integration (VLSI) presents difficult design and development problems due to the ease with which errors creep into the process. It can require several passes through the design and development cycle to eliminate the errors. A laser tool has been developed that makes connections between two levels of metallization separated by an insulator on a VLSI chip. A programmable logic array (PLA) was developed in conjunction with the laser tool. The PLA is programmed to perform a complex logic function by means of the laser tool. A short movie shows the tool in operation programming a PLA. The PLA contains the equivalent of 600 circuits worth of logic, which can be programmed in a few minutes. It is thus possible to construct a complex system with a relatively few PLA modules in a short time.

Test set size minimization and fault detection effectiveness: A case study in a space application

The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.