A Testing Strategy for PLAs

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure.

A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation. >

Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can’t be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced. >

Programmable logic arrays (PLA) are highly regular circuits which compute suitable Boolean functions. PLAs are a popular circuit design especially in microcontrollers. PLA folding is a technique for minimizing the area of such PLA. Folding can be formulated in purely graph-theoretic terms. In this paper, we study PLA for a very special class of Boolean functions, namely indicator functions of intervals of binary numbers. As a possible application, we can imagine PLA which shall supervise that an input value lies in a prescribed tolerance interval. From a mathematical point of view, the connection of these interval indicator functions with threshold graphs and cographs is interesting. Our study naturally leads to the folding problem in cographs which is shown to be solvable in linear time. In sections 1-2 we introduce the basic notions. In section 3 we prove a theorem on minimal normal forms of interval indicator functions, thereby motivating the folding problem on cographs. A linear time algorithm solving this problem is derived in section 4. Finally, in section 5, we mention some related results and possible directions of further research.

Programmable array logic (PAL) devices can be used for realising both combinational and sequential circuits. The final behaviour of a PAL chip is determined by the fuse pattern in this chip. The paper presents a systematic procedure for generating a minimal test set to examine whether a programmed chip functions as expected. The upper bound of the size of a test set generated by the proposed procedure is also derived. >

The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.

A decomposition of a programmable logic array (PLA) into two cascaded PLAs is considered. The problem is divided into two subproblems: a partition problem, which finds the partition of the input variables, and an encoding problem, which finds an encoding of signals between two PLAs. Multiple-valued decomposition theory is used to find a good partition of the input variables. Experimental results show that serial decomposition reduces the total PLA size by 10% to 30%. >

Very large scale integration (VLSI) presents difficult design and development problems due to the ease with which errors creep into the process. It can require several passes through the design and development cycle to eliminate the errors. A laser tool has been developed that makes connections between two levels of metallization separated by an insulator on a VLSI chip. A programmable logic array (PLA) was developed in conjunction with the laser tool. The PLA is programmed to perform a complex logic function by means of the laser tool. A short movie shows the tool in operation programming a PLA. The PLA contains the equivalent of 600 circuits worth of logic, which can be programmed in a few minutes. It is thus possible to construct a complex system with a relatively few PLA modules in a short time.

The increasing recognition of PLA's as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA's is the class of contact faults. A single contact fault is the spurious presence or absence of a contact between a row and a column of a PLA. We consider in this paper the problem of determining the capability of complete single contact fault test sets to cover multiple contact faults of PLA's. Our approach consists of developing a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA. Using this model, it is shown that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in a PLA. Applications of this model to stuck-at fault diagnosis are also discussed.

The authors present algorithms for Boolean decomposition, which decompose a two-level logic function into a cascade of smaller two-level logic functions, such that the overall area of the resulting logic network is minimized. The algorithms are based on multiple-valued minimization. Given a PLA (programmable logic array), a subset of inputs to the PLA is selected. This selection step incorporates a novel algorithm which selects a set of inputs such that the cardinality of the multiple-valued cover, produced by representing all combinations of these inputs as different values of a single multiple-valued variable, is much smaller than the original binary cover cardinality. A relatively small size for the multiple-valued cover implies that the number of good Boolean factors contained in this subset of inputs are re-encoded to satisfy the constraints given in the multiple-valued cover, thus producing a binary cover for the original PLA whose cardinality equals the multiple-valued cover cardinality. >

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Various implementations of the quantum-dot cellular automata (QCA) device architecture may help many performance scaling trends continue as we approach the nanoscale. Experimental success has led to the evolution of a research track that looks at QCA-based design. This paper follows that track and looks at <emphasis emphasistype="italic">implementation friendly</emphasis>, programmable QCA circuits. Specifically, we present a novel QCA-based programmable logic array (PLA) structure. Our PLA is capable of providing defect tolerance at both the device and architectural levels, and limits the amount of determinism required in any fabrication process. The design is compact, exploits properties unique to QCA devices in order to ease programmability, and is relevant to all implementations of the QCA. </para>

The authors consider the problems associated with on-chip testing of programmable logic arrays (PLAs) which are deeply embedded in VLSI systems. A detailed summary of the built-in logic block observer (BILBO) approach to embedded PLA testing is given. Then, an innovative method for on-chip testing, which makes use of the input/output registers of the PLA as test aids, is presented. This method is less area-consuming than the traditional BILBO technique. >

A regular structure and capability to implement arbitrary logic functions in a two-level logic form have placed crossbar-based programmable logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting logic tautology in two-level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost

In this paper, a greedy approach for minimizing the area of a programmable logic array (PLA) using column folding of combinational component of finite state machines (FSMs) is presented. Also, the row reordering problem is addressed and a simple data structure is proposed to satisfy the constraints imposed by folding of columns. Genetic algorithm based formulation has been used for state encoding which gives minimally reduced two-level PLAs. Results obtained for several MCNC benchmark circuits show area improvement of 16.7% over NOVA[9], 53.1% over KISS[8] and 12.3% over STARF[7] on an average.