Testability analysis of hierarchical finite state machines

Sharing intellectual property (IP) blocks in today's competitive market poses significant high security risks. In this paper, we present a tutorial for a watermarking approach based on the embedding of the ownership proof as part of the IP design's finite state machine (FSM). It utilizes coinciding as well as unused transitions in the state transition graph of the design. Based on this approach, we have developed a robust watermarking framework, used for copyright protection. The developed technique increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. In order to integrate these algorithms in the design cycle of industrial projects, we extend the above techniques to enable the watermarking of hierarchical finite state machines (HFSMs)

This paper presents a model for building agents' memories in virtual environments. This approach allows the generation of agents' memory during the simulation, without user intervention. Moreover the memory can be used to generate behavioural reactive rules. We use dynamic and hierarchical finite state machine (DHFSM) in order to represent the agents past experiences.

Events detection and handling based on hierarchical finite state machines in EAST PCS

Verification of scope-dependent hierarchical state machines

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

A new fast PWM modulation strategy for power electric converter based on finite set state machine theory

The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept of a semi-synchronous FSM that combines the benefits of both synchronous and asynchronous state machines. The result is a FSM which runs at high clock frequency, consumes very little power and can be implemented, verified and tested as a synchronous FSM. This concept has been used to design a PFM FSM in a field programmable gate array (FPGA) and in a 65 nm CMOS technology.

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

In the manufacturing process, digital twin technology can provide real-time mapping, prediction, and optimization of the physical manufacturing process in the information world. In order to realize the complete expression and accurate identification of and changes in the real-time state of the manufacturing process, a digital twin framework of incremental learning driven by stream data is proposed. Additionally, a novel method of stream data-driven equipment operation state modeling and incremental anomaly detection is proposed based on the digital twin. Firstly, a hierarchical finite state machine (HFSM) for the manufacturing process was proposed to completely express the manufacturing process state. Secondly, the incremental learning detection method driven by stream data was used to detect the anomaly of the job process data, so as to change the job status in real time. Furthermore, the F1 value and time consumption of the proposed algorithm were compared and analyzed using a general dataset. Finally, the method was applied to the practical case development of a welding manufacturer’s digital twin system. The flexibility of the proposed model is calculated by the quantitative method. The results show that the proposed state modeling and anomaly detection method can help the system realize job state mapping and state change quickly, effectively, and flexibly.

A model for a phased-array radar in the context of a defensive Naval system has been developed using hierarchical finite state machines. This model is used to study resource management for a fleet of ships equipped with one radar unit each. This fleet is under attack from aerial enemy agents. A control algorithm formulated on this specific model is used to dynamically generate a greedy policy for radar operation. The defense system is evaluated in its capability to acquire and track those aerial threats, in two configurations -centralized and decentralized (independent). The performance is quantified on the basis of time taken to establish the threat trajectory, time to compute the policy and the number of threats the system fails to track. A comparison of performance in the two configurations is provided.

(Self-)reconfigurable finite state machine (FSM) had been introduced as a formal model to implement the sequential circuit which can be reconfigured during the operation. The reconfiguration is initiated by the external events or by the controller that generates the reconfiguration transitions. In this paper, we optimize the number of reconfiguration transitions required to reconfigure a given FSM into a new target FSM. A serious limitation of previously proposed techniques is that they depend on the number of essential transitions which are the different transitions between a given and a target FSMs. In this paper, we propose a new technique based on FSM decomposition to decompose a given and target FSMs into two sub machines. A part of essential transitions is implemented as a single decomposed submachine with the same functionality in two decomposed FSMs. This submachine is inactive and has no effect in the normal operation but reduces the number of essential transitions during the reconfiguration. We give a decomposition strategy, realize the proper hardware, and provide a set of experimental results that shows the reconfiguration transitions can be substantially reduced, in some cases up to 54%

In this paper we outline a theory for the environment-modeling problem , the problem of abstracting component finite state machines (FSMs)bordering a particular FSM of interest within a network of interacting FSMs. The goal is to lay a theoretical foundation for the automatic state reduction of large FSM networks. We feel this is a prerequisite for the efficient use of many verification techniques. We focus on computing conditions for the safe removal of a component FSM in a FSM network, where removal is safe if it preserves a certain well-defined trace equivalence. We present an optimized algorithm for determining language universality of a FSM, as well as determining independence of a FSM from those of its inputs connected to outputs of neighboring FSMs. These two properties, input independence and language universality, provide the necessary and sufficient conditions for safe removal. In addition, we show how simulation relations can be utilized, both to reduce the cost of computing safe removal and to create an appropriate abstract FSM when safe removal is not possible.

Perkembangan industri game mendorong kebutuhan akan sistem kendali karakter dan pertarungan yang responsif dalam genre Action RPG 2D. Penelitian ini bertujuan untuk mengimplementasikan sistem character player yang mencakup character controller dan combat system menggunakan Godot Engine. Character controller dirancang untuk memberikan kendali yang halus terhadap pergerakan karakter seperti bergerak, berlari, dan melompat, sedangkan combat system difokuskan pada mekanisme attack, deteksi musuh, upgrade stats, dan pengurangan damage musuh. Metode yang digunakan adalah rekayasa perangkat lunak dengan tahapan analisis, perancangan, implementasi, dan pengujian. Sistem kendali karakter dikembangkan menggunakan Hierarchical Finite State Machine (HFSM) agar modular dan mudah dikembangkan, sedangkan sistem pertarungan memanfaatkan area dan animasi yang sinkron. Hasil pengujian menunjukkan bahwa sistem berjalan dengan baik dan memberikan pengalaman bermain yang responsif dan stabil. Implementasi ini penting sebagai acuan pengembangan game Action RPG 2D berbasis open-source.

Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test generation, and fault coverage. Finite state machines (FSMs) are commonly used for specifying controllers. FSMs may have shortcomings in modeling complex systems. With the introduction of X-machines, complex systems can be modeled at higher levels of abstraction. An X-machine can be converted into an FSM while preserving the level of abstraction. The fault coverage of a test sequence for an FSM specification provides a confidence level. We propose a fault coverage metric for an FSM specification based on the transition fault model, and using this metric, we derive the coverage of a test sequence. The article also presents a method which generates short test sequences that meet a specific coverage level and then extends this metric to determine the coverage of a test sequence for an FSM driven by an FSM network. We applied our FSM verification technique to a real-life FSM, namely, the fibre channel arbitrated loop port state machine, used in the field of storage area networks.

This paper presents a model specifying requirements of real-time systems. Different from existing researches, this model mainly uses rules and templates to represent hierarchical FSMs (Finite State Machine). In this model, one rule corresponds to one state transition of FSM and one template corresponds to one FSM. Rules and information with respect to a FSM can be written in a template. So templates include not only state diagrams, but also information that can not be described by FSM, such as performance requirements. The specification using this model consists of a collection of templates and it is easy for users to understand and to review. After introduced the related researches and principles of the model, this paper specifies requirements of a real-time system with this model, and discusses characters of this model in the end.