The delay of circuits whose inputs have specified arrival times

ON SOME CLASSES OF BI-UNIVALENT FUNCTIONS

We propose a scalable efficient parameterized block-based statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. As a preprocessing step, we employ an independent component analysis to transform the set of correlated non-Gaussian parameters to a basis set of parameters that are statistically independent. Given the moments of the variational parameters, we use a Pade acute-approximation-based moment-matching scheme to generate the distributions of the random variables representing the signal arrival times and preserve correlation information by propagating arrival times in a canonical form. Our SSTA procedure is able to generate the circuit delay distributions with reasonably small prediction errors. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99%, 2.05%, 2.33%, and 2.36%, respectively, in the mean, standard deviation, and 5% and 95% quantile points of the circuit delay. Experimental results show that our procedure can handle as many as 256 correlated non-Gaussian variables in about 5 min of runtime. For a circuit with |G| gates and a layout with g spatial correlation grids, the complexity of our approach is O(g|G|) .

A checking test for a monotone read-once function f depending essentially on all its n variables is a set of vectors M distinguishing f from all other monotone read-once functions of the same variables. We describe an inductive procedure for obtaining individual lower and upper bounds on the minimal number of vectors T(f) in a checking test for any function f. The task of deriving the exact value of T(f) is reduced to a combinatorial optimization problem related to graph connectivity. We show that for almost all functions f expressible by read-once conjunctive or disjunctive normal forms, T(f) ~n / ln n. For several classes of functions our results give the exact value of T(f).

In [9], the notion of c-differentials was introduced as a potential expansion of differential cryptanalysis against block ciphers utilizing substitution boxes. Drawing inspiration from the technique of higher order differential cryptanalysis, in this paper we propose the notion of higher order c-derivatives and differentials and investigate their properties. Additionally, we consider how several classes of functions, namely the multiplicative inverse function and the Gold function, perform under higher order c-differential uniformity.

Have decidual natural killer (dNK) cells a different microRNA (miRNA or miR) expression pattern compared to NK cells circulating in the peripheral blood (pb) of healthy pregnant women in the first trimester of gestation? dNK cells have a unique miRNA profile, showing exclusive expression of a set of miRNAs and significant up- or down-regulation of most of the miRNAs shared with pbNK cells. dNK cells differ from pbNK cells both phenotypically and functionally, and their origin is still debated. Many studies have indicated that miRNAs regulate several important aspects of NK cell biology, such as development, activation and effector functions. Decidua basalis and peripheral blood specimens were collected from women (n = 7) undergoing voluntary termination of gestation in the first trimester of pregnancy. dNK and pbNK cells were then highly purified by cell sorting. miRNAs expression was analysed by quantitative RT-PCR (qRT-PCR)-based arrays using RNA purified from freshly isolated and highly purified pbNK and dNK cells. Results from arrays were validated by qRT-PCR assays. The bioinformatics tool ingenuity pathway analysis (IPA) was applied to determine the cellular network targeted by validated miRNAs and the correlated biological functions. Herein, we identified the most differentially expressed miRNAs in NK cells isolated from peripheral blood and uterine decidua of pregnant women. We found that 36 miRNAs were expressed only in dNK cells and two miRNAs only in pbNK cells. Moreover, 48 miRNAs were commonly expressed by both NK cell preparations although at different levels: 28 were upregulated in dNK cells, while 15 were downregulated compared to pbNK cells. Validation of a selected set (n = 11) of these miRNAs confirmed the differential expression of nine miRNAs: miR-10b and miR-214 expressed only in dNK cells and miR-200a-3p expressed only in pbNK cells; miR-130b-3p, miR-125a-5p, miR-212-3p and miR-454 were upregulated while miR-210-3p and miR-132 were downregulated in dNK cells compared to pbNK cells. IPA network analysis identified a single network connecting all the miRNAs as well as their significant involvement in several classes of functions: 'Organismal injury, Reproductive system disease, Inflammatory disease' and 'Cellular development'. These miRNAs target molecules such as argonaute 2, tumour protein p53, insulin and other genes that belong to the same network and significantly influence cell differentiation and pregnancy. In the present study, the cellular network and biological functions modulated by miRNAs differentially expressed in dNK and pbNK cells were identified by IPA considering only molecules and relationships that were with confidence 'experimentally observed' in leucocytes. The decidual and pbNK cells that were analysed here are a heterogeneous population and further study will help to disentangle whether there are differences in miRNA production by the different subsets of NK cells. This is the first study describing a different miRNA expression profile in dNK cells compared to matched pbNK cells during the first trimester of pregnancy. Our findings improved the body of knowledge on dNK cell biology and strongly suggest further investigation into the roles of miRNAs that are differentially expressed in human dNK compared to pbNK cells. Our results suggest that specific miRNAs can modulate dNK cell origin and functions, highlighting a potential role of this miRNA signature in human development and diseases. This work was supported by grants from the Istituto Pasteur, Fondazione Cenci Bolognetti, the European NoE EMBIC within FP6 (Contract number LSHN-CT-2004-512040), Istituto Italiano di Tecnologia, and Ministero dell'Istruzione, dell'Università e della Ricerca (Ricerche Universitarie), and from Università Politecnica delle Marche. There are no conflicts of interest to declare.

On the tractability of the Brownian Bridge algorithm

Many voting systems consist of a set of players who can form coalitions; a winning coalition is one that can pass a measure. The winning and losing coalitions can be given by several classes of functions, including switching functions, threshold functions, weighted voting systems, and simple games. We define a zonotope T n T_n related to these functions and describe its coordinates in terms of a measure of voting power. We also give a voting interpretation of the coordinates of the derived zonotope T ¯ n \bar {T}_n .

Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter- and intra-die variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32% on average over all test cases.

We consider the eigenvalue problem associated with the Dunkl-type differential operator (in which the reflection operator R is involved)in the context of supersymmetric quantum mechanical models. By solving this eigenvalue problem with the help of known exactly solvable potentials, we construct several classes of functions satisfying certain orthogonality relations. We call them the Dunkl-supersymmetric (Dunkl-SUSY) orthogonal functions. These functions can be expressed in terms of the classical orthogonal polynomials. The key feature of these functions is that they appear by pairs, i.e. Qn(x) and Qn(−x) are both the eigenfunctions of . A general formulation of the Dunkl-SUSY orthogonal polynomials is also presented.

Let varGamma (x) denote the classical Euler gamma function. The logarithmic derivative psi (x)=[ln varGamma (x)]'=frac{varGamma '(x)}{ varGamma (x)}, psi '(x), and psi ''(x) are, respectively, called the digamma, trigamma, and tetragamma functions. In the paper, the authors survey some results related to the function [psi '(x)]^{2}+ psi ''(x), its q-analogs, its variants, its divided difference forms, several ratios of gamma functions, and so on. These results include the origins, positivity, inequalities, generalizations, completely monotonic degrees, (logarithmically) complete monotonicity, necessary and sufficient conditions, equivalences to inequalities for sums, applications, and the like. Finally, the authors list several remarks and pose several open problems.

As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions for reducing variations. From statistical static timing analysis in circuit level and performance evaluation in processor level, this paper tries to unveil how efficiently instruction cascading improves performance yield of processors. Cascading instructions increases logic depth and decreases the standard deviation of the circuit delay. That might improve performance yield of microprocessors. Unfortunately, however, it is found that variability reduction in the circuit level does not always mean yield enhancement in the microarchitecture level.

An accurate prediction of circuit delay distribution is essential to verify the timing closure of digital circuits and to estimate the parametric yield. In the presence of process variations, the most accurate technique for circuit delay prediction is using Monte Carlo simulations. However, to get an accurate estimate, a large number of Monte Carlo simulations are required which is infeasible in the case of large circuits. Although statistical timing analysis techniques are widely used to predict the circuit delay distribution in a reasonable run time, the standard deviation of circuit delay is often inaccurate. In this work, an efficient technique for circuit delay prediction using limited number of Monte Carlo simulations is proposed. This is done using the concept of Bayesian inference with the results from statistical timing analysis as the prior information. The results indicate that combining statistical timing analysis along with limited number of Monte Carlo simulations increases the accuracy of prediction of circuit delay variance. The number of Monte Carlo simulations can be decided based on the accuracy requirements or run time constraints.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post‐mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology‐independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area‐ or delay‐optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area‐optimized circuits and 38% in case of delay‐optimized circuits are achievable. The post‐mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.