The future of computing is mobile

With the rapid development of smart grid technology, load regulation on the demand side has become a flexible approach for load peak shaving and renewable energy accommodation. In this paper, an optimal wind power consumption strategy is proposed based on the time series analysis of electricity load. In view of the periodicity of residential load on both working days and non-working days, the double seasonal ARIMA model is applied to predict users' behavior and the adjustable electricity load for wind power consumption. In addition, the difference between residential load and wind power generation is taken as the objective function for optimal power consumption. The problem of wind energy consumption is solved by prioritizing residential load according to the correlation between the load series and wind power series in each time slot. Experimental results demonstrated the reliability and accuracy of the proposed algorithm.

Gesture control of mobile devices is an emerging user interaction modality. Large-scale deployment has been delayed by two main technical challenges: detecting gestures reliably and power consumption. There have also been user-experience- related challenges, such as indicating the start of a gesture, social acceptance, and feedback on the gesture detection status. This chapter evaluates a solution for the main challenges: an event-based movement interaction modality, tapping, that emphasizes minimal user effort in interacting with a mobile device. The technical feasibility of the interaction method is examined with a smartphone equipped with a sensor interaction cover, utilizing an enabling software framework. The reliability of detecting tapping is evaluated by analyzing a dataset collected with the smartphone prototype. Overall, the results suggest that detecting tapping is reliable enough for practical applications in mobile computing when the interaction is performed in a stationary situation.

Gesture control of mobile devices is an emerging user interaction modality. Large-scale deployment has been delayed by two main technical challenges: detecting gestures reliably and power consumption. There have also been user-experience-related challenges, such as indicating the start of a gesture, social acceptance, and feedback on the gesture detection status. This chapter evaluates a solution for the main challenges: an event-based movement interaction modality, tapping, that emphasizes minimal user effort in interacting with a mobile device. The technical feasibility of the interaction method is examined with a smartphone equipped with a sensor interaction cover, utilizing an enabling software framework. The reliability of detecting tapping is evaluated by analyzing a dataset collected with the smartphone prototype. Overall, the results suggest that detecting tapping is reliable enough for practical applications in mobile computing when the interaction is performed in a stationary situation.

Smart home technology has recently expanded due to advancements in wireless network sensors and mobile devices. A smart home is a home that is comprised of devices that can interact with each other and be controlled remotely via mobile applications. Smart home devices include smart bulbs, smart switches, smart plugs, smart TVs, and surveillance cameras. Employing such devices and applications could lead to some usability issues if usability is not taken into consideration during the development phase of the smart home technology. This paper investigates the usability of the TP-link smart plug and its smartphone application. The data was collected from pre- and post-test questionnaires, observation during tests, and post-test interviews. The findings show that linking the smart plug to the application was somewhat difficult, but using the smart plug was generally easy. Furthermore, recommendations were suggested to enhance the interface of the smart plug's smartphone application.

The development and design of electronic components with a reliable lifespan has become one of the most important challenges in usage of mechanical engineering, air transport, and medical spheres. It is obvious that these systems must be very reliable. To reduce area and power consumption as well as to increase the speed, the technological process is scaled. This scale forces to take into account phenomena in sub-micron technological processes, that could be ignored in technological processes greater than 90 nm due to their small impact. Thus, for submicron technological processes, the circuit design must be done by considering the aging phenomena. In this paper, it is proposed a method which is used to compensate the frequency reduction in the voltage controlled oscillator (VCO) due to aging degradation. As a result of the proposed method the frequency reduction due to the influence of aging phenomena was decreased from 6.5% to 0.31%.

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s/spl times/4 ch) has been developed by using 0.25-/spl mu/m CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s.

This thesis focuses on the low noise amplifier design of RF receivers for WLAN 802.11a/b/g dual-band and 60GHz applications, in which we cover the topics including introduction to bands and applications, literature review, circuit designs, chips’ measurement results and discussions of the results. There are four chapters to discourse on the basis of low noise amplifier design, and circuit implementations. In Chapter 1, we introduce the wireless RF system, IEEE 802.11 bands, and optical transmission and wireless communications systems development. In Chapter 2, important parameters of LNA are described, including introduction, impedance matching theory, matching network design, noise figure, linearity, and stability. Chapter 3 is focused on the design of a sub 1V CMOS low noise amplifier for dual-band application. This chapter starts from studying three basic topologies for LNA, including their matching design and noise ability. Then we use low voltage characteristics of the folded cascode circuit to design a low power consumption circuit for 2.4GHz/5GHz dual band application. The chip is implemented using TSMC 0.18um CMOS process technology. The measured peak gains are 13.9 dB and 9.6dB at frequencies 2.4GHz and 5GHz, respectively. The measured noise figures are 3.9 dB and 4.7 dB, respectively, for both bands. The power consumption of the circuit is 5.5mW under 1V supply voltage. The subject of Chapter 4 is the 60GHz low noise amplifier design using GaAs process technology, and probing the technology behavior of the GaAs process and its applications. This chip is fabricated using WIN 0.15um pHEMT process. The measured peak gain of this 60GHz GaAs LNA is 11dB at 55.7GHz, and the measured noise figure is 4.8dB. The power consumption of the circuit is 26.6mW under 1.8V supply voltage. In Chapter 5, a 60GHz LNA using TSMC 90nm CMOS process technology is presented. The measurement results show a 6.57 dB gain and a 7.4 dB noise figure at 59GHz. The power consumption of the circuit is 9.4mW under 1.2V supply voltage.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

The explosive growth in the number of mobile devices such as Internet-enabled cellular phones, wireless handheld devices, wireless laptops, and tablet PCs has driven the corresponding growth in applications for mobile computing. These applications usually belong to one of two classes: collaborative applications and individual application. While collaborative applications require several mobile devices to work together and include peer-to-peer computing and grid computing, individual applications are local to the mobile device and its user. In this paper, we present a framework that allows mobile devices to collaboratively work on a computationally-expensive problem. Such a problem is decomposed into smaller tasks and distributed across other mobile devices willing to share their computational power with others. This framework is based on the paradigm of grid computing applied to the domain of wireless mobile devices. This paper presents our current implementation of the framework architecture and simulation of its functionality. Also, we focus on the issues of mobility, QoS and network stability and their effect on the performance of our collaborative problem-solving framework.

With the shrinking integrated circuits (IC) technology and the popularity of portable electronic devices, power dissipation has become a critical issue in very large scale integrated (VLSI) circuits design. To reduce the power dissipation, much attention had been drawn to the techniques in process technology, circuits level, gates level and register-transfer (RT) level. However, from the experience with the traditional approach, it is clear that system level design optimization have the greatest influence on power consumption. And hence, power optimization techniques in system level are able to gain considerable power reduction, compared with techniques in other level. In this review, some general state-of-art system-level low power techniques are tested and reviewed, and some guidelines for system level low power design are generalized.

Energy harvesting techniques emerge as a potential solution for prolonging the lifetime of the energy-constrained mobile wireless devices. In this paper, we focus on radio frequency (RF) energy harvesting for multiuser multicarrier mobile wireless networks. The mobile users are capable of harvesting energy from the dedicated subcarriers over which they are communicating with the base station in addition to harvesting ambient RF signals. We propose a joint data and energy transfer optimization framework for powering mobile wireless devices through RF energy harvesting while minimizing the overall power consumption. The proposed framework determines the optimal power resources that need to be allocated to meet data rate requirements of downlink and uplink communications. Simulations show that substantial power savings are achieved by allowing the ambient RF energy harvesting as well as by exploiting the different system parameters.

Considerable attention has been given to automating the design of electronic circuits during the last decade. The principal areas of research and development include: (1) simulation, timing verification and fault modeling, (2) placement, routing and partitioning, (3) silicon compilers, and (4) hardware description languages. Computer-aided-design systems have been recently introduced based on the above research. Techniques have also been developed for mapping numerical algorithms onto highly parallel architectures that are well suited for fabrication as VLSI/VHSIC chip sets. Design rule checkers may also be used to verify that a design meets a specified set of physical implementation constraints prior to fabrication. In this paper, these hardware design automation techniques will be surveyed to determine the state-of-the-art in this important area of computer-aided-design.

The article provides an overview of the design features of rotor-pulsation devices in which the method of discrete-pulse energy input is implemented – a method of intensification of heat and mass exchange processes, which contributes to the development and implementation of energy-saving technologies in various industries. The idea of DPEI is to accumulate the energy previously distributed in the working volume in a stationary and arbitrary state in local discrete points of the system and then implement it in pulses to achieve the necessary thermophysical effects. Non-traditional methods of intensification of heat and mass exchange processes by means of discrete-pulse energy input into discrete environments formed the basis of new technologies for obtaining emulsions of various types. In many industries and everyday life, emulsions of various types are widely used, which leads to a constant increase in the requirements for their quality, first of all, stability and uniformity. Therefore, there is a high need for the development of highly efficient equipment and the determination of rational technological modes for processing “liquid-liquid” systems. In the Institute of Technical Thermophysics of the National Academy of Sciences of Ukraine, equipment was created, the principle of which is to implement the DPEI method, in particular, rotary-pulsation apparatus (RPA). Rotary-pulsation devices (RPA) are highly efficient, small-sized equipment for creating homogeneous mixtures of various liquids with a wide range of applications. With the help of RPA, issues are optimally solved in many technological processes, such as: dispersion, emulsification, mixing and homogenization of various systems, namely powdery, liquid, multicomponent, high and low viscosity media in many industries. The most important indicator of RPA performance is the size of dispersed emulsion particles obtained after processing in RPA from a mechanical mixture of mutually insoluble liquids or components that are difficult to mix.

"Radio Design in Nanometer Technologies" addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. To that end, the book contains three parts: Part 1 is a general part discussing current and future wireless networks, chipset evolution over the past decade and ending with a discussion on radio requirements for software defined radio(SDR). Part 2 will focus on the digital baseband of a wireless chip set, flexible DSP cores for multi-standard wireless platforms and system-on-chip SoC implementation and design flow issues. Part 3 will be devoted to radio design issues starting at the transceiver level and going down to discuss critical issues facing design of future multi band multi standard radios for emerging wireless standards such as UMTS, WiMaX, MIMO and WLAN in a way that is consistent with the prevailing vision of SDR. As such, the book is the first volume that looks at the integrated radio design problem as a 'piece of a big puzzle', namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today's increasingly complex wireless systems

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits ( rms ) for high-performance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18µm and 1.2V 90nm).