The Improved Frequency Response Function and its Effect on Modal Circle Fits

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

An OFDMA based channel access scheme is proposed for dynamic spectrum access to utilize frequency spectrum efficiently. Though the OFDMA based scheme is flexible enough to change the bandwidth and channel of the transmitted signals, the OFDMA signal has large PAPR (Peak to Average Power Ratio). In addition, if the OFDMA receiver does not use a filter to extract sub-carriers before FFT (Fast Fourier Transform) processing, the designated sub-carriers suffer large interference from the adjacent channel signals in the FFT processing on the receiving side. To solve the problems such as PAPR and adjacent channel interference encountered in the OFDMA based scheme, this paper proposes a novel dynamic channel access scheme using overlap FFT filter-bank based on single carrier modulation. It also shows performance evaluation results of the proposed scheme by computer simulation.

Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are the key computation block in Orthogonal Frequency Division Multiplexing (OFDM) system. They dominate most of the areas and power dissipation in implementation therefore efficient low-power and high-throughput implementation of FFT processor is essential for successful deployment of OFDM based system. High-throughput and Low-power 128-point FFT Processor is designed using Radix-25 algorithm to reduce computation complexity and the feedforward pipeline architecture [called Multipath Delay Commutator (MDC)] with four data path for providing higher throughput. This architecture is more hardware-efficient than Multipath parallel feedback (MDF) design, which makes them attractive for the computation of FFT in most demanding applications. The proposed FFT processor uses improved Digit slice multiplier for complex multiplication. This proposed FFT processor is designed using Verilog and implemented using 180 nm CMOS Technology with supply voltage of 1.8v. The result shows significant reduction in power consumption in comparison with existing design and increasing throughput with area trade off.

The experimental environments for impact tests are simple to construct compared to other vibration tests in experimental modal analysis. However, given that sufficient sampling time is necessary for the response to attenuate, the following two problems arise: The first is that work efficiency is lowered. The second is that the measurement time increases, which makes it more susceptible to noise. To solve these problems, it is common to shorten the sampling time and apply an exponential window to reduce the leakage error of the frequency response function (FRF). Although studies on the influence on the FRF exist, identification accuracy for damping characteristic and the influence on the residue have not discussed. In this study, the influence on the modal properties obtained and the accuracy of the results are clarified using numerical examples based on a circle fit and method using simultaneous equations of the real and imaginary parts of the FRF. Finally, the identification results were compared and made sure that the method using simultaneous equations of the real and imaginary parts of FRF can identify modal properties with high accuracy. This method is effective for improving the working efficiency and reducing the influence of noise.

In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements. A 1k-32k flexible FFT core is implemented in the Altera FPGA, results show that our proposed scheme is suitable for applications where flexible large size FFT processor is needed such as digital video broadcasting, wireless networks etc.

There exist Fast Fourier transform (FFT) algorithms, called dimensionless FFTs, that work independent of dimension. These algorithms can be configured to compute different dimensional DFTs simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows us to design an FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this paper we design a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow, and show how to map different dimensionless FFTs onto this hardware design. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. Using a performance model we search for the optimal algorithm for the family of processors we considered. The resulting algorithm and corresponding hardware design was implemented using FPGA.

This paper presents fully parallel fast Fourier transform (FFT) processor for coherent optical OFDM system. It has a length of 256. For processing of 100 Gb/s throughput it has parallel input and output structure. FFT processor has 32 radix-16 processor with trivial multiplication and consists of an array structure in parallel arithmetic processing. We designed and implemented the proposed FFT processor using Xilinx FPGA XCVU190. The result shows 205,530 LUTs and the maximum throughput is 46.592 Giga-Samples/sec.

In this brief, a high-throughput and low-complexity fast Fourier transform (FFT) processor for wideband orthogonal frequency division multiplexing communication systems is presented. A new indexed-scaling method is proposed to reduce both the critical-path delay and hardware cost by employing shorter wordlength. Together with the mixed-radix multipath delay feedback structure, the proposed FFT processor can achieve very high throughput with low hardware cost. From analysis, it is shown that the proposed indexed-scaling method can save at least 11% memory utilizations compared to other state-of-the-art scaling algorithms. Also, a test chip of a 1.2 Gsample/s 2048-point FFT processor has been designed using UMC 90-nm 1P9M process with a core area of 0.97 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The signal-to-quantization-noise ratio (SQNR) performance of this test chip is over 32.7 dB to support 16-QAM modulation and the power consumption is about 117 mW at 300 MHz. Compared to the fixed-point FFT processors, about 26% area and 28% power can be saved under the same throughput and SQNR specifications.

With the upcoming fourth generation wireless systems and convergence of multiple radio standards into a single terminal, building blocks are needed that can be configured for computing various algorithms used in different standards. Given these trends and requirements, in our previous paper we successfully proposed a circuit-sharing design for the DAB receiver to integrate the FFT (fast Fourier transform) and IMDCT (inverse modified discrete cosine transform) operations into the same functional circuit. The proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. To further improve the efficiency of our previous work, this investigation proposes another alternative design named the circuit-sharing pipeline design (CSPD) using a single processor with a pipeline scheme to combine two functions, FFT and IMDCT, into the same circuit. The proposed method reduces the required chip area and cost of DAB receivers. Analyzing the existing relationship among IMDCT, DCT (discrete cosine transform) and FFT, the IMDCT function can be replaced using a FFT function. Therefore, it is not necessary to design an extra circuit for IMDCT. The arithmetic unit in the FFT processor can be significantly reduced due to employing the pipeline scheme. Consequently, the circuit redundancies in the IMDCT and FFT functions can be easily eliminated to allow exploitation of the decreased chip area. Results of this study demonstrate that the proposed design can provide advantages such as low gate count and small memory size in the DAB (digital audio broadcasting) receiver.

This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 &#956;m ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.

In this paper, a new design method for small point fast Fourier transform (FFT) processor is proposed in order to satisfy the increased demands for low resource and power consumption in addition to high real-time performance in communication and control systems. Using 64 point FFT with radix-2, decimation in time (DIT) algorithm as the design objective, only an adder block and a multiplier block with pipeline structure and floating point arithmetic are adopted applying this design method. According to different classifications of twiddle factor, corresponding butterfly operations can be implemented to save the total calculation time to only 1100 clock cycles for 64 point FFT. In addition, multiple FFT processor blocks can be integrated for parallel computing to achieve higher data throughput rate. Compared with some other designs of 64 point FFT, the final results show that the proposed design has better real-time performance and lower system level complexity with the same amount of resources.

Fast Fourier Transform (FFT) processors, having a significant impact on the performance of communication systems, have been a hot topic of research for many years. FFT function consists of consecutive multiply-add operations over complex numbers, dubbed as butterfly units. Use of redundant number systems is a way of increasing the speed of FFT coprocessors. It eliminates carry-propagation and hence permits latency reduction of each stage of the pipelined FFT architecture. This paper proposes a high-speed FFT processor using the devised fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on Binary-Signed-Digit (BSD) representation. Three-operand BSD adder and BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and in the parallel BSD multiplier, so as to improve the speed of the FDPA unit. Moreover, modified-booth encoding is used to accelerate the BSD multiplier. Synthesis results show that the proposed design is about two times faster than the best previous work; but at cost of more area/power consumption.

Chapter 7 focuses upon response of continuous systems. The shear beam is used as the prime example. As a previous chapters, deterministic vibration via modal solutions initiates the subject. Stationary and concentrated random excitation follow in order. The author touches upon random vibration of a thin plate. Our next topic is the alternative solution of shear beams, where again, the uncoupled SDOF systems are applied in either time or frequency domain. The random vibration of a dam reservoir system subjected to vertical ground acceleration is exploited. The alternative impulse response function solves the dam problem where the hydrodynamic pressure cor­ responds to the shear force. The frequency response function and power spectral density response conclude this section. In a similar manner, the dam-reservior is excited by a horizontal acceleration simulating an earthquake event. A very good chapter! The next chapter covers the design of structures for random excitations. The stationary Gaussian process (random variable) is defined. The probability of upcrossings over a specified level and probability density of the peaks introduce this phase of the subject. The author applies this to the con­ cept of structural design against yield failure using an SDOF and a dam-reservoir subjected to vertical ground acceleration. The chapter concludes with structural damage against fatigue and includes the Palmgren-Miner (PM) rule and stationary narrow band random loading. The reviewer would have preferred seeing actual random test data since PM is limited as to excitations and may be unconservativ e at times. Chapter 9 treats nonstationary response which is a time dependent response of structures. Beginning with an SDOF system having stationary excitation, we again utilize the damreservoir system (vertical acceleration excitation). This con­ tinues into systems with nonstationary excitation containing Priestley's complex integral model. Zero damped and lightly damped SDOF systems inaugurate this topic. An alternative approach is Bendat and Piersol's model which employs the autocorrelation function for zero mean excitation and nonsta­ tionary specturm. The dam-reservoir with nonstationary ex­ citation concludes the chapter. The last chapter develops random vibration of structures in the plastic range. The random walk model is the eye-opener. It encompasses basic probability definitions (mass probability, mass function, conditional probability) and then derives the Chapman-Kalmagarov-Smolchoewski equation applied to structural response. Application of random walk model to a nonlinear structure and solution of the Fokker-Plunck equa­ tion complete the chapter. The appendices include Fast Fourier Transform (FFT) in random vibration and Monte Carlo simulation plus references. In summary, this is a good book. The author spares no ef­ fort in making the reader understand random vibration. The