The Nexus Approach to Integrating Multithreading and Communication

Runtime Mechanisms for Efficient Dynamic Multithreading

Proof-carrying code (PCC) is a general framework that can, in principle, verify safety properties of arbitrary machine-language programs. Existing PCC systems and typed assembly languages, however, can only handle sequential programs. This severely limits their applicability since many real-world systems use some form of concurrency in their core software. Recently Yu and Shao proposed a logic-based "type" system for verifying concurrent assembly programs. Their thread model, however, is rather restrictive in that no threads can be created or terminated dynamically and no sharing of code is allowed between threads. In this paper, we present a new formal framework for verifying general multi-threaded assembly code with unbounded dynamic thread creation and termination as well as sharing of code between threads. We adapt and generalize the rely-guarantee methodology to the assembly level and show how to specify the semantics of thread "fork" with argument passing. In particular, we allow threads to have different assumptions and guarantees at different stages of their lifetime so they can coexist with the dynamically changing thread environment. Our work provides a foundation for certifying realistic multi-threaded programs and makes an important advance toward generating proof-carrying concurrent code.

It is difficult to map the execution model of multithreading languages (languages which support fine-grain dynamic thread creation) onto the single stack execution model of C. Consequently, previous work on efficient multithreading uses elaborate frame formats and allocation strategy, with compilers customized for them. This paper presents an alternative cost-effective implementation strategy for multithreading languages which can maximally exploit current sequential C compilers. We identify a set of primitives whereby efficient dynamic thread creation and switch can be achieved and clarify implementation issues and solutions which work under the stack frame layout and calling conventions of current C compilers. The primitives are implemented as a C library and named StackThreads. In StackThreads, a thread creation is done just by a C procedure call, maximizing thread creation performance. When a procedure suspends an execution, the context of the procedure, which is roughly a stack frame of the procedure, is saved into heap and resumed later. With StackThreads, the compiler writer can straightforwardly translate sequential constructs of the source language into corresponding C statements or expressions, while using StackThreads primitives as a blackbox mechanism which switches execution between C procedures.

We implement a new sequentialization algorithm for multi-threaded C programs with dynamic thread creation as a new CSeq module. The novel basic idea of this algorithm is to fix (by a nondeterministic guess) the sequence of write operations in the shared memory and then simulate the behavior of the program according to any scheduling that respects this choice. Simulation is done thread-by-thread and the thread creation mechanism is replaced by function calls.

Step-Indexed Kripke Model of Separation Logic for Storable Locks

We propose a sound, complete, and automatic method for pairwise reachability analysis of higher-order concurrent programs with recursion, nested locks, joins, and dynamic thread creation. The method is based on a reduction to higher-order model checking (i.e., model checking of trees generated by higher-order recursion schemes). It can be considered an extension of Gawlitz et al.’s work on the join-lock-sensitive reachability analysis for dynamic pushdown networks (DPN) to higher-order programs. To our knowledge, this is the first application of higher-order model checking to sound and complete verification of (reasonably expressive models of) concurrent programs.

We introduce ω-Petri nets (ωPN), an extension of plain Petri nets with ω-labeled input and output arcs, that is well-suited to analyse parametric concurrent systems with dynamic thread creation. Most techniques (such as the Karp and Miller tree or the Rackoff technique) that have been proposed in the setting of plain Petri nets do not apply directly to ωPN because ωPN define transition systems that have infinite branching. This motivates a thorough analysis of the computational aspects of ωPN. We show that an ωPN can be turned into a plain Petri net that allows to recover the reachability set of the ωPN, but that does not preserve termination. This yields complexity bounds for the reachability, (place) boundedness and coverability problems on ωPN. We provide a practical algorithm to compute a coverability set of the ωPN and to decide termination by adapting the classical Karp and Miller tree construction. We also adapt the Rackoff technique to ωPN, to obtain the exact complexity of the termination problem. Finally, we consider the extension of ωPN with reset and transfer arcs, and show how this extension impacts the decidability and complexity of the aforementioned problems.

The paper investigates the evaluating task of the traffic as the registered number of vehicles of one of the three classes (a bus, passenger car or truck) that passed in a certain direction per unit of time, according to data from CCTV cameras in real time. For simplification this problem solving was divided into three components. They are registration of traffic flow objects and their classification, finding trajectories of fixed objects and determining traffic lanes, as well as counting objects in each direction. A comparative analysis of the existing algorithms, software and hardware systems that solve problems similar to the problems was carried out; also, a proprietary approach was proposed. The analysis describes the feasibility for developing their own approach due to the lack of an algorithm that meets all the requirements, such as estimating the traffic on the basis of data from surveillance cameras. Besides, the existing hardware and software systems are of the high cost and complexity. The YOLO artificial neural network was used to recognize objects on the frame in the form of rectangles containing the image of a vehicle. To build tracks, objects are compared frame-by-frame based on a set of characteristics, including a simple (average) perceptual hash and the coordinates of the corresponding rectangle. The developed algorithm for constructing trajectories of moving traffic objects, highlighting lanes of automobile traffic and counting vehicles is proposed as a software module. The testing results concerning the quality of the algorithm are introduced. The main advantages and disadvantages of the proposed approach are highlighted.

Reachability Analysis of Synchronized PA Systems

Unified Memory in heterogeneous systems serves a wide range of applications. However, limited capacity of the device memory becomes a first order performance bottleneck for data-intensive general-purpose applications with increasing working sets. The performance overhead under memory oversubscription depends on the memory access pattern of the corresponding workload. While a regular application with sequential, dense memory access suffers from long latency write-backs, performance of a irregular application with sparse, seldom access to large data-sets degrades due to page thrashing. Although smart spatio-temporal prefetching and large page eviction yield good performance in general, remote zero-copy access to host-pinned memory proves to be beneficial for irregular, data-intensive applications. Further, new generation GPUs introduced hardware access counters to delay page migration and reduce memory thrashing. However, the responsibility of deciding what strategy is the best fit for a given application relies heavily on the programmer based on thorough understanding of the memory access pattern through intrusive profiling. In this work, we propose a programmer-agnostic runtime that leverages the hardware access counters to automatically categorize memory allocations based on the access pattern and frequency. The proposed heuristic adaptively navigates between remote zero-copy access to host-pinned memory and first-touch page migration based on the trade-off between low latency remote access and high-bandwidth local access. We show that although designed to address memory oversubscription, our scheme has no impact on performance when working sets fit in the device-local memory. Experimental results show that our scheme provides performance improvement of 22% to 78% for irregular applications under 125% memory oversubscription compared to the state of the art. At the same time, regular applications are not impacted by the framework.

Digital image correlation (DIC) method is a rapid development of photomechanics technology. The basic principle of the method is calculated the correlation between before and after deformation of the specimen surface speckle images, which is used to determine displacement and deformation. DIC measurement system includes hardware and software system. The former is the speckle image acquisition system, the latter are speckle image analysis algorithm and implementation procedures. Because the software analysis algorithm can achieve sub-pixel accuracy or even more, most of scholars have focused on the speckle image analysis algorithms. The system performance caused by the composition of hardware system has been less introduced. The hardware system mainly included the camera, lenses, lighting and other components. If hardware system is not perfect and stable, it will bring hundreds or even thousands of micro strain measurement error. These unfavorable factors make 2D-DIC inaccurate in small deformation tests. To some extent, it limits the application of 2D-DIC in the engineering practice. This paper analyzed that the various components of DIC hardware system impacted on the system performance, It was given that how to reasonably select the various components in the typical cases, as well as involved that the selection of 2D-DIC measurement system is applied to the actual engineering measurements in high temperature environment. These can provide support that 2D-DIC measurement system is better applied to the engineering practice.

After a deep analysis on how to use an image processing system to detect the missing holes on the motor carling, we design the whole system combined with the actual production conditions of the motor carling. Afterwards we explain the whole system's hardware and software in detail. We introduce the general functions for the system's hardware and software. Analyzed these general functions, we discuss the modules of the system's hardware and software and the theory to design these modules in detail. The measurement to confirm the area to image processing, edge detection, randomized Hough transform to circle detecting is explained in detail. Finally, the system result tested in the laboratory and in the factory is given out.

An integrated hardware and software system is used in studying neural correlates of learning. The hardware system is designed to maximize experimental flexibility, while the software system is designed to maximize computer speed for data acquisition and programmer efficiency for data analysis.

Autonomous underwater vehicles (AUVs) have many, scientific, military, and commercial applications because of their potential capabilities and significant cost-performance improvements. Typical AUV development requires critical system design and many costly at-sea trials during which systems specifications can be validated. Modeling and simulation provides a cost-effective method for carrying out preliminary component or system (hardware and software) testing and verification. Due to the complexity of most AUV development and their tight schedules, the simulated systems often differ considerably from the actual embedded architecture, thereby reducing the fidelity of the entire simulation. We adopted a hardware-in-the-loop (HIL) simulation approach that includes some level of the system's hardware and software. As expected, an HIL simulation requires all components be run under hard real-time constraint. The paper presents our implementation and considerations on HIL simulation for single and multiple vehicles. A brief mention of sensor and environment modeling is also provided.

Modern commodity hardware architectures, with their multiple multi-core CPUs and high-speed system interconnects, exhibit tremendous power. In this paper, we study performance limitations when building both software routers and software virtual routers on such systems. We show that the fundamental performance bottleneck is currently the memory system, and that through careful mapping of tasks to CPU cores, we can achieve forwarding rates of 7 million minimum-sized packets per second on mid-range server-class systems, thus demonstrating the viability of software routers. We also find that current virtualisation systems, when used to provide forwarding engine virtualisation, yield aggregate performance equivalent to that of a single software router, a tenfold improvement on current virtual router platform performance. Finally, we identify principles for the construction of high-performance software router systems on commodity hardware, including full router virtualisation support.