Runtime Mechanisms for Efficient Dynamic Multithreading

This paper considers Rigel, a programmable accelerator architecture for a broad class of data- and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled single-program, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a task-centric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and/or restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications.We perform a design analysis of Rigel to quantify the compute density and power efficiency of our initial design. We find that Rigel can achieve a density of over 8 single-precision GFLOPS/mm2in 45nm, which is comparable to high-end GPUs scaled to 45nm. We perform experimental analysis on several applications ported to the Rigel low-level programming interface. We examine scalability issues related to work distribution, synchronization, and load-balancing for 1000-core accelerators using software techniques and minimal specialized hardware support. We find that while it is important to support fast task distribution and barrier operations, these operations can be implemented without specialized hardware using flexible hardware primitives.

It is difficult to map the execution model of multithreading languages (languages which support fine-grain dynamic thread creation) onto the single stack execution model of C. Consequently, previous work on efficient multithreading uses elaborate frame formats and allocation strategy, with compilers customized for them. This paper presents an alternative cost-effective implementation strategy for multithreading languages which can maximally exploit current sequential C compilers. We identify a set of primitives whereby efficient dynamic thread creation and switch can be achieved and clarify implementation issues and solutions which work under the stack frame layout and calling conventions of current C compilers. The primitives are implemented as a C library and named StackThreads. In StackThreads, a thread creation is done just by a C procedure call, maximizing thread creation performance. When a procedure suspends an execution, the context of the procedure, which is roughly a stack frame of the procedure, is saved into heap and resumed later. With StackThreads, the compiler writer can straightforwardly translate sequential constructs of the source language into corresponding C statements or expressions, while using StackThreads primitives as a blackbox mechanism which switches execution between C procedures.

Proof-carrying code (PCC) is a general framework that can, in principle, verify safety properties of arbitrary machine-language programs. Existing PCC systems and typed assembly languages, however, can only handle sequential programs. This severely limits their applicability since many real-world systems use some form of concurrency in their core software. Recently Yu and Shao proposed a logic-based "type" system for verifying concurrent assembly programs. Their thread model, however, is rather restrictive in that no threads can be created or terminated dynamically and no sharing of code is allowed between threads. In this paper, we present a new formal framework for verifying general multi-threaded assembly code with unbounded dynamic thread creation and termination as well as sharing of code between threads. We adapt and generalize the rely-guarantee methodology to the assembly level and show how to specify the semantics of thread "fork" with argument passing. In particular, we allow threads to have different assumptions and guarantees at different stages of their lifetime so they can coexist with the dynamically changing thread environment. Our work provides a foundation for certifying realistic multi-threaded programs and makes an important advance toward generating proof-carrying concurrent code.

We implement a new sequentialization algorithm for multi-threaded C programs with dynamic thread creation as a new CSeq module. The novel basic idea of this algorithm is to fix (by a nondeterministic guess) the sequence of write operations in the shared memory and then simulate the behavior of the program according to any scheduling that respects this choice. Simulation is done thread-by-thread and the thread creation mechanism is replaced by function calls.

Step-Indexed Kripke Model of Separation Logic for Storable Locks

The Nexus Approach to Integrating Multithreading and Communication

We propose a sound, complete, and automatic method for pairwise reachability analysis of higher-order concurrent programs with recursion, nested locks, joins, and dynamic thread creation. The method is based on a reduction to higher-order model checking (i.e., model checking of trees generated by higher-order recursion schemes). It can be considered an extension of Gawlitz et al.’s work on the join-lock-sensitive reachability analysis for dynamic pushdown networks (DPN) to higher-order programs. To our knowledge, this is the first application of higher-order model checking to sound and complete verification of (reasonably expressive models of) concurrent programs.

We introduce ω-Petri nets (ωPN), an extension of plain Petri nets with ω-labeled input and output arcs, that is well-suited to analyse parametric concurrent systems with dynamic thread creation. Most techniques (such as the Karp and Miller tree or the Rackoff technique) that have been proposed in the setting of plain Petri nets do not apply directly to ωPN because ωPN define transition systems that have infinite branching. This motivates a thorough analysis of the computational aspects of ωPN. We show that an ωPN can be turned into a plain Petri net that allows to recover the reachability set of the ωPN, but that does not preserve termination. This yields complexity bounds for the reachability, (place) boundedness and coverability problems on ωPN. We provide a practical algorithm to compute a coverability set of the ωPN and to decide termination by adapting the classical Karp and Miller tree construction. We also adapt the Rackoff technique to ωPN, to obtain the exact complexity of the termination problem. Finally, we consider the extension of ωPN with reset and transfer arcs, and show how this extension impacts the decidability and complexity of the aforementioned problems.

Multithreading is an important technique that improves processor utilization by allowing computation to be overlapped with the long latency operations that commonly occur in multiprocessor systems. This paper presents register relocation, a new mechanism that efficiently supports flexible partitioning of the register file into variable-size contexts with minimal hardware support. Since the number of registers required by thread contexts varies, this flexibility permits a better utilization of scarce registers, allowing more contexts to be resident, which in turn allows applications to tolerate shorter run lengths and longer latencies. Our experiments show that compared to fixed-size hardware contexts, register relocation can improve processor utilization by a factor of two for many workloads.

Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techniques have been shown to increase speed, but at great cost as designs include prediction tables, selection logic, and a confidence mechanism. This paper proposes compiler-controlled value prediction optimizations that obtain good speedups while keeping hardware costs low. The branch predictor is used to estimate the confidence of the value predictor for speculated instructions. This technique obtains 4.6% speedup when completely implemented in software and 15.2% speedup when minimal hardware support (a 1 KB predictor table) is added. We also explore the use of critical path information to aid in the selection of value prediction candidates. The key result of our study is that programs with long dynamic dependence chains benefit with this technique while programs with shorter chains benefit more so from simple selection methods that favor optimization frequency. A new branch instruction that ignores innocuous value mispredictions is shown to eliminate unnecessary mispredictions when program semantics aren't violated by confidence branch mispredictions.

article Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine Share on Authors: David E. Culler View Profile , Anurag Sah View Profile , Klaus E. Schauser View Profile , Thorsten von Eicken View Profile , John Wawrzynek View Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 19Issue 2Apr. 1991 pp 164–175https://doi.org/10.1145/106975.106990Online:01 April 1991Publication History 212citation1,194DownloadsMetricsTotal Citations212Total Downloads1,194Last 12 Months13Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Reachability Analysis of Synchronized PA Systems

This research focuses on the development and implementation of a web-based citizen data management system in Keboan Anom Village, Sidoarjo, Indonesia. The aim of the study is to enhance the efficiency and effectiveness of citizen data recording and management processes. The System Development Life Cycle (SDLC) Waterfall model is employed as the methodology for system development, ensuring an organized and systematic approach. Data collection involves semi-structured interviews and unstructured observations, targeting the village's RT 01 (neighborhood association) officials. The application features two key functions: citizen registration, including permanent and non-permanent residents, and a comprehensive data summary. Access to these functions is limited to the RT Secretary and the RT Chairman. The implementation of the system provides improved data management and financial tracking capabilities, enabling simplified reporting. The web-based platform ensures accessibility for RT officials and residents with internet connectivity. Black box testing confirms the functionality of the website and its compliance with expected outputs. The results demonstrate that the application supports the transformation of Keboan Anom Village into a more efficient and technologically connected Digital Village. Future research is suggested to examine community participation levels in using the citizen data management application and its impact on decision-making and overall village governance, incorporating participatory approaches to understand the perspectives and active involvement of Keboan Anom Village residents.
 Highlight:
 
 Efficient citizen data management: The development of a web-based application for citizen data management in Desa Keboan Anom enables efficient recording and documentation of resident information, improving data accuracy and accessibility.
 Technological transformation: The implementation of the web-based system contributes to the realization of a Digital Village concept, facilitating efficient and technology-connected administration in Desa Keboan Anom, Sidoarjo.
 Participatory approach: Future research should focus on evaluating community participation levels and the impact of the citizen data management application on decision-making and overall village governance, utilizing a participatory approach to gain insights and foster active involvement of Keboan Anom Village residents.
 
 Keyword:
 Keboan Anom Village, Citizen Data Management, Web-Based Application, Efficiency, Participatory Approach

This study aims to analyze the implementation of a mobile web-based academic information system with an Enterprise Architecture Planning (EAP) approach using SWOT (Strengths, Weaknesses, Opportunities, Threats) analysis. A mobile web-based academic information system is an urgent need in the world of education to improve the efficiency of data management and academic services. With the EAP model, this study maps business, data, application, and technology needs to ensure the development of an integrated system that is oriented to organizational needs. SWOT analysis is used to identify strengths, weaknesses, opportunities, and threats in the implementation of this system. The results of the study indicate that the main strengths lie in the ease of accessibility and efficiency of data management, while weaknesses include limited human resources in understanding new technologies. Opportunities include the development of digital technology and the need for flexible academic services, while threats come from data security challenges and resistance to technological change. These findings are expected to contribute to the development of a more effective mobile web-based academic information system implementation strategy that is in accordance with the needs of educational organizations. This study also provides recommendations for management decision making to maximize the potential of the system by minimizing possible risks.

Fault-injection experiments on the instruction-set architecture level are commonly used to analyze embedded software's susceptibility to hardware faults, typically involving a vast number of experiments with systematically varying fault locations and times. Determinism and high performance are the predominant requirements on fault-injection platforms. Injecting faults into a real embedded hardware platform instead of a simulator is favorable for both workload execution speed and result accuracy. The most performance-critical part of such a fault-injection platform is the “fast forward” operation, which executes the target machine code without faults until the exact dynamic instruction is reached at which the execution must be stopped to inject the next fault. Unfortunately, most embedded CPUs do not support this operation efficiently. In this paper we present an approach that speeds up fast-forwarding significantly for most workloads with minimal requirements on hardware support. Based on a previously recorded instruction trace - which is needed for systematic fault-injection experiment planning anyways - we use standard debugging hardware to advance to a chosen point in program execution with a minimal number of steps. We evaluate our FAIL* tool platform with two MiBench benchmark categories, and improve experiment throughput by up to several magnitudes compared to similar fault-injection tools in the field.