Rigel

Runtime Mechanisms for Efficient Dynamic Multithreading

Multithreading is an important technique that improves processor utilization by allowing computation to be overlapped with the long latency operations that commonly occur in multiprocessor systems. This paper presents register relocation, a new mechanism that efficiently supports flexible partitioning of the register file into variable-size contexts with minimal hardware support. Since the number of registers required by thread contexts varies, this flexibility permits a better utilization of scarce registers, allowing more contexts to be resident, which in turn allows applications to tolerate shorter run lengths and longer latencies. Our experiments show that compared to fixed-size hardware contexts, register relocation can improve processor utilization by a factor of two for many workloads.

Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techniques have been shown to increase speed, but at great cost as designs include prediction tables, selection logic, and a confidence mechanism. This paper proposes compiler-controlled value prediction optimizations that obtain good speedups while keeping hardware costs low. The branch predictor is used to estimate the confidence of the value predictor for speculated instructions. This technique obtains 4.6% speedup when completely implemented in software and 15.2% speedup when minimal hardware support (a 1 KB predictor table) is added. We also explore the use of critical path information to aid in the selection of value prediction candidates. The key result of our study is that programs with long dynamic dependence chains benefit with this technique while programs with shorter chains benefit more so from simple selection methods that favor optimization frequency. A new branch instruction that ignores innocuous value mispredictions is shown to eliminate unnecessary mispredictions when program semantics aren't violated by confidence branch mispredictions.

article Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine Share on Authors: David E. Culler View Profile , Anurag Sah View Profile , Klaus E. Schauser View Profile , Thorsten von Eicken View Profile , John Wawrzynek View Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 19Issue 2Apr. 1991 pp 164–175https://doi.org/10.1145/106975.106990Online:01 April 1991Publication History 212citation1,194DownloadsMetricsTotal Citations212Total Downloads1,194Last 12 Months13Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Modern network processors deliver a set of methods for implementing critical sections. A number of them rely on specific hardware support and capabilities, while software techniques are still available when hardware support is not flexible enough. Network processors are dedicated to packet processing and their main goal is to achieve the best possible packet processing performance. Therefore, when choosing the implementation method for a particular problem that will be protected by a critical section, the aim must me for the method to influence the overall system performance A wrongly implemented critical section can very easily degrade the level of parallelism and in consequence the performance of the whole system. Sometimes even correctly implemented critical sections can negatively impact the speed of paths that do not need to be protected with a critical section.

This paper presents a system that recognizes a limited vocabulary of spoken words in a speaker-independent manner. The system requires only minimal hardware support for acoustic preprocessing. In contrast to other approaches to word-level recognition, it reduces the information content of the speech signals by a compression algorithm before presenting them as inputs to a standard 3-layer backpropagation network. The network learns to recognize the utterances of the speakers in the training set, and the trained network is then used to recognize the spoken words of unknown speakers. Recognition rates of up to 91% were obtained for unknown speakers of the same sex and up to 72% for a mix of both male and female speakers. Since the training times are fast and the system is very cost effective, the approach is practically feasible for a variety of applications.

The bit-by-bit reproducibility of floating-point results, which is defined by the IEEE 754 standard, prohibits optimizations such as reassociation and the use of native operations such as fused multiply-add (FMA), and thus it significantly impairs floating-point performance. Recent network-oriented languages such as Java strictly conform to the standard, and thus their numerical computing performance becomes inherently lower than conventional languages.In this paper, we propose a new software technique, called floating-point (FP) speculation, to optimize floating-point performance while preserving the bit-by-bit reproducibility of the results. We execute the fast unsafe code and the slow verification code in parallel. The unsafe code does not wait for the verification code, and is immediately followed by the subsequent code that uses the probable result from the unsafe code assuming the speculation will succeed. The improvement from FP speculation results from this earlier start of the subsequent code.Unlike other speculation techniques, FP speculation does not require any special instructions or hardware support. Rather, it exploits unused floating-point registers and execution units. Therefore it is generally applicable for processor architectures that have sufficient floating-point resources.

Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMware ® Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization.We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution.We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization.

Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMware ® Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization.We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution.We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization.

The computational complexity of FFT (Fast Fourier Transform) processing in an OFDM (Orthogonal Frequency Division Multiplex) based receiver is large with a large amount of receiver antennas. In LTE (Long Term Evolution) release 8, FFTs of different size are used for user data and random-access preambles [1] requiring additional FFTs to be implemented for random-access reception. Within the current paper, a 5G random-access preamble format is proposed based on a short sequence of the same length as the length of the OFDM symbols that are used for other uplink physical channels, such as user data, control signaling, and reference signals. The preamble sequence is constructed by repeating the short sequence multiple times. A corresponding preamble detector in which FFTs of the same size as for other uplink channels and signals are used is also described. In this way, the amount of special random-access related processing and hardware support is significantly reduced for multi-antenna systems with frequency-domain beamforming. This preamble detector is also robust against inter-carrier interference from other uplink channels and signals. Furthermore, the proposed preamble detector scheme can be used in 5G scenarios with a high amount of phase noise and frequency errors. For time-domain beamforming, the beamforming weights can be changed during preamble reception such that the number of spatial directions is increased for which preamble detection is done. Simulation results are used to compare preamble formats for different lengths of the sequences.

Combining the benefits of Thread level speculation (TLS) and Transactional memory (TM) can enhance the performance of chip multiprocessor (CMP) effectively. This paper proposes a novel speculative transactional memory architecture “SPT” that supports both TLS&TM semantics, including its special hardware, compiler and execution support. It further trades off several important factors in the multicore architecture design. The experimental results show that 16 cache lines is the proper speculative buffer capacity and the write back strategy is the better cache design choice in speculation.

Traditional development of reliable device drivers for multiprocessor system on chip (MPSoC) is a complex and demanding process, as it requires interdisciplinary knowledge in the fields of hardware and software. This problem can be alleviated by an advanced driver generation environment. We have achieved this by systematically synthesizing drivers from a device features model and specifications of hardware and in-kernel interfaces, thereby lessening the impact of human error on driver reliability and reducing the development costs. We present the methodology called Me3D and confirm the feasibility of the driver generation environment by manually converting sources of information captured in different formalisms to a Multimedia Card Interface (MCI) driver for a real MPSoC under a lightweight operating system (OS).

Until recently, the most software development tools and techniques were concentrated on views from the sequential model of program execution. Software developers who only familiarize with the sequential model will face unusual challenges of software projects that require multi-core or parallel programming. In this paper, we addresses the challenges that developers face as their projects requiring multi-core or parallel programming by applying design patterns. In general, design patterns are usually regarded as the role of quality-improver for improving software quality, but they could be the role of design-facilitator for facilitating design activities. To address this issue, we propose an approach for specifying the applicable contexts and refactoring steps of patterns systematically, as well as automating the refactoring process for lightening the burden of developers. We also extract a multi-core pattern ParallelWhile which is derived from the template class parallel_while of Intel ® TBB library to introduce our approach. Furthermore, we demonstrate our approach by a real-world multicore embedded system PVE (Parallel Video Encoder), where Command Pipeline pattern is designed for the design enhancement and platform migration. It aids developers identifying operations which could be parallel processing, and revising a sequential design as an Intel ® TBB parallel structure. In addition, our approach can promote the extensibility of parallel operations.

Machine Learning (ML) is becoming a ubiquitous technology employed in many real-world applications in diverse areas such as agriculture, human health, entomology, and engineering. In some applications, sensors measure the environment while supervised ML algorithms are responsible for interpreting these data to make an automatic decision. Generally, these devices face three main restrictions: power consumption, cost, and lack of infrastructure. Most of these challenges can be better addressed by embedding ML classifiers in the hardware that senses the environment. Thus, we need highly-efficient classifiers suitable to execute in unresourceful hardware. However, this scenario conflicts with the state-of-practice of ML, in which classifiers are frequently implemented in high-level interpreted languages (e.g., Java or Python), make unrestricted use of floating-point operations and assume plenty of resources such as memory, processing and energy. In this work, we present a software tool named Embedded Machine Learning (EmbML) that implements a pipeline to develop classifiers for low-power microcontrollers. This pipeline starts with learning a classifier in a desktop or server computer using popular software packages or libraries as WEKA or scikit-learn. EmbML converts the classifier into a carefully crafted C++ code with support for resource-constrained hardware, such as the avoidance of unnecessary use of main memory and implementation of fixed-point operations for non-integer numbers. Our experimental evaluation on benchmark datasets and a variety of microcontrollers shows that EmbML classifiers achieve competitive results in terms of accuracy, classification time, and memory cost. Compared to classifiers from some existing related tools, ours achieved the best time and memory performances in at least 70% of the cases. Lastly, we conduct experiments in a real-world application to describe the complete pipeline for using EmbML and assessing its classifiers with an intelligent trap to classify and capture flying insects.

We introduce an environment we've developed that helps designers represent, model, and explore design tradeoffs at the architectural abstraction level and synthesize designs at the behavioral level. The Design Analysis and Synthesis Environment (DASE) accomplishes this by supporting design capture, design space exploration, and validation for the final design synthesis. DASE specifically caters to design capture via the Design Specification Language (DSL) description, exploration through simulation, and behavioral synthesis through a translator that produces VHDL output for behavior synthesis. DASE has a support library for telecommunication systems, although DASE's library support system can he reconfigured for other domains. We illustrate the various capabilities of DASE, such as specification capture, design exploration, software and hardware modeling, and synthesis. We discuss models based on Petri nets, summarize other DASE designs, and present results reflecting synthesized code sizes-the resulting executable descriptions of the hardware and software. >