The reduction of threading dislocations in GaN using a GaN nanocolumn interlayer

ABSTRACTWe have studied the possibilities of reducing the threading dislocation (TD) density in GaAs on Si using free side wall growth on patterned Si substrates and/or using a soft ZnSe interlayer in combination with post growth annealing procedures. TD densities were accurately determined using large area plan view TEM and were found to be unaffected by proximity to free side walls and by the ZnSe interlayer. Post growth heat treatments led to a factor of ∼2 reduction in TD density and to bunching of dislocations throughout the thickness of the film.

Low threading dislocation Ge on Si by combining deposition and etching

GaN/sapphire layers have been grown by Metal Organic Vapour Phase Epitaxy (MOVPE). An amorphous silicon nitride layer is deposited using a SiH4/NH3 mixture prior to the growth of the low temperature GaN buffer layer. Such a process induces a 3D nucleation at the early beginning of the growth, resulting in a kind of maskless ELO process with random opening sizes. This produces a significant decrease of the threading dislocation (TD) density compared to the best GaN/sapphire templates. Ultra Low Dislocation density (ULD) GaN layers were obtained with TD density as low as 7×107cm−2 as measured by atomic force microscopy (AFM), cathodoluminescence and transmission electron microscopy (TEM). Time-resolved photoluminescence experiments show that the lifetime of the A free exciton is principally limited by capture onto residual donors, similar to the situation for nearly dislocation-free homoepitaxial layers.

Evolution of threading dislocations in MOCVD-grown GaN films on (1 1 1) Si substrates

The effect of varying threading dislocation densities on the internal quantum efficiencies (IQEs) of InGaN quantum wells (QWs), with and without intentionally created “V-pits,” is reported here. InGaN QW samples grown on GaN-on-sapphire templates with threading dislocation densities of <1 × 108 and <1 × 109 cm−2 are compared, with and without GaN/InGaN superlattice (SL) layers incorporated to intentionally open up the threading dislocation cores and form large-size “V-pits.” The formation of “V-pits” is confirmed by cross-sectional transmission electron microscopy to initiate from threading dislocations in the SL layers. The densities of the pits are confirmed by plan-view SEM to agree with the substrate threading dislocation densities. The experimental room temperature IQEs of the “V-pit” QW samples are enhanced to 15% ± 1% compared to 6% ± 2% for conventional QW samples. Both conventional and “V-pit” samples show insensitivity to the magnitude of the dislocation densities with respect to IQE performance, while the “V-pit” samples show shifts in the peak emission wavelengths compared to the conventional samples, attributed to strain modulation. This study provides additional understanding of the causes of the observed insensitivity of the IQEs to different threading dislocation densities.

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si 0.8Ge 0.2 pseudo-substrates

The detrimental effects of structural defects, micro-twins (MTs) and threading dislocations (TDs), on electron mobility have been investigated for InSb quantum wells (QWs) at room temperature (RT). The constants that are necessary to calculate the electron-mobility limits of these defects were determined by a least-squares-based method that has an advantage of clear representation of the analytical results in a two-dimensional space. Based on a mathematical consideration, a general method of converting electron-mobility limits into percentage impacts upon the total electron mobility was developed. Percentage-mobility-impact analyses showed that, when InSb QWs grown on on-axis (001) GaAs substrates have a TD density of 8.7 × 108 – 3.2 × 109/cm2, 21–14 and 18–45% of electron-mobility degradation are attributed to MTs and TDs, respectively, at RT. The use of 2° off-axis (001) GaAs substrates reduces MT densities in InSb QWs, resulting in a suppression of the MT mobility impact to 3–2% and a complementary slight increase of the TD mobility impact to 22–51% in the same TD density range. This considerable TD mobility limit indicates that it should be possible to improve RT electron mobility in InSb QWs grown on 2° off-axis (001) GaAs substrates, by means of reducing TD density further (< 8.7 × 108/cm2). Although the mobility impacts due to phonons in InSb QW grown on-axis and 2° off-axis (001) GaAs substrates are 54–36 and 67–42%, respectively, phonon scattering is not a single dominant scattering factor: MTs and TDs have also substantial negative impacts upon RT electron mobilities in InSb QWs.

Characterisation of defects in p-GaN by admittance spectroscopy

This work investigates the role of threading dislocation densities (TDD) in the low density regime on the vertical transport in Si0.06Ge0.94 heterostructures integrated on Si(001). The use of unintentionally doped Si0.06Ge0.94 layers enables the study of the impact of grown-in threading dislocations (TD) without interaction with processing-induced defects originating, e.g., from dopant implantation. The studied heterolayers, while equal in composition, the degree of strain relaxation, and the thickness feature three different values for the TDD as 3 × 106, 9 × 106, and 2 × 107 cm−2. Current–voltage measurements reveal that leakage currents do not scale linearly with TDD. The temperature dependence of the leakage currents suggests a strong contribution of field-enhanced carrier generation to the current transport with the trap-assisted tunneling via TD-induced defect states identified as the dominant transport mechanism at room temperature. At lower temperatures and at high electric fields, direct band-to-band tunneling without direct interactions with defect levels becomes the dominating type of transport. Leakage currents related to emission from mid-gap traps by the Shockley–Read–Hall (SRH) generation are observed at higher temperatures (>100 °C). Here, we see a reduced contribution coming from SRH in our material, featuring the minimal TDD (3 × 106 cm−2), which we attribute to a reduction in point defect clusters trapped in the TD strain fields.

Effect of the V/III ratio during buffer layer growth on the yellow and blue luminescence in undoped GaN epilayer has been studied by means of photoluminescence spectroscopy and high resolution X-ray diffraction. It is found that the densities of screw and edge threading dislocations increase with the V/III ratio of the buffer layer, and the intensities of the yellow luminescence (YL) and blue luminescence (BL) emissions also increase dramatically. However, the density ratio of the edge threading dislocation to the screw threading dislocation remains invariant, as well as the intensity ratio of YL emission to BL emission. It can be concluded from these phenomena that the edge threading dislocation and screw threading dislocation can enhance the YL and BL emissions, respectively.

Threading dislocation reduction in (0 0 01) GaN thin films using SiN x interlayers

High-resolution X-ray diffraction analysis on HVPE-grown thick GaN layers

A correlation between bulk leakage current density and threading dislocation density in silicon–germanium mesa-isolated diodes fabricated on relaxed graded buffer layers is presented. Si0.75Ge0.25 p-i-n diodes were grown on SiGe graded buffers with different grading rates. Graded buffers with different grading rates yielded “virtual substrates” with varying densities of threading dislocations. Bulk leakage current densities were differentiated from surface leakage currents by using p-i-n diodes with different areas. We demonstrate that the increase in bulk leakage current density in SiGe p-i-n diodes can be modeled by generation processes assisted by deep levels related to threading dislocations.

Line, point and surface defect morphology of graded, relaxed GeSi alloys on Si substrates

This paper reports on a new approach for reducing the threading dislocation density in GaAs on Si. We have used InxGa1-xAs/GaAs strained-layer superlattices (SLSs) grown on GaAs/Si at 300°C by migration-enhanced epitaxy as threading dislocation barriers. Different from conventional high-temperature-grown SLSs, the low-temperature-grown SLSs are only slightly relaxed by misfit dislocation formation at GaAs/SLS interfaces. Thus, considerable strain can be accumulated in SLS. In addition, new threading dislocation generation due to the misfit dislocation can be suppressed. These factors lead to effective threading dislocation bending and to significant reduction in the dislocation density. For the samples with a SLS of x=0.3, the average etch-pit density is 7×104 cm-2, which is the lowest value ever reported.