The use of error detection and compensation techniques for testing the integer class cBigNumber

To avoid catastrophic events like unrecoverable system failures on mobile and embedded systems caused by soft-errors, software-based error detection and compensation techniques have been proposed. Methods like error-correction codes or redundant execution can offer high flexibility and allow for application-specific fault-tolerance selection without the needs of special hardware supports. However, such software-based approaches may lead to system overload due to the execution time overhead. An adaptive deployment of such techniques to meet both application requirements and system constraints is desired. From our case study, we observe that a control task can tolerate limited errors with acceptable performance loss. Such tolerance can be modeled as a (m,k) constraint which requires at least m correct runs out of any k consecutive runs to be correct. In this paper, we discuss how a given (m,k) constraint can be satisfied by adopting patterns of task instances with individual error detection and compensation capabilities. We introduce static strategies and provide a formal feasibility analysis for validation. Furthermore, we develop an adaptive scheme that extends our initial approach with online awareness that increases efficiency while preserving analysis results. The effectiveness of our method is shown in a real-world case study as well as for synthesized task sets.

Error detection is a fundamental need in most computer networks and communication systems in order to combat the effect of noise. Error detection techniques have also been incorporated with lossless data compression algorithms for transmission across communication networks. In this paper, we propose to incorporate a novel error detection scheme into a Shannon optimal lossless data compression algorithm known as Generalized Luröth Series (GLS) coding. GLS-coding is a generalization of the popular Arithmetic Coding which is an integral part of the JPEG2000 standard for still image compression. GLS-coding encodes the input message as a symbolic sequence on an appropriate 1D chaotic map Generalized Luröth Series (GLS) and the compressed file is obtained as the initial value by iterating backwards on the map. However, in the presence of noise, even small errors in the compressed file leads to catastrophic decoding errors owing to sensitive dependence on initial values, the hallmark of deterministic chaos. In this paper, we first show that repetition codes, the oldest and the most basic error correction and detection codes in literature, actually lie on a Cantor set with a fractal dimension of }{} frac{1}{n} , which is also the rate of the code. Inspired by this, we incorporate error detection capability to GLS-coding by ensuring that the compressed file (initial value on the chaotic map) lies on a Cantor set. Even a 1-bit error in the initial value will throw it outside the Cantor set, which can be detected while decoding. The rate of the code can be adjusted by the fractal dimension of the Cantor set, thereby controlling the error detection performance.

In computer communication and telecommunication applications, error detection and correction techniques must be employed to ensure a reliable data transmission from the source to the destination. Two of the most prevailing techniques, Cyclic Redundancy Check (CRC) detection and Hamming code correction, are implemented and analyzed. The CRC method picks up prominence because it joins three focal points: extraordinary blunder identification capacities, minimal overhead, and simplicity of usage. Moreover, both the CRC and Hamming code are binary linear codes. However, one significant difference is that Hamming code only works on data of some fixed size (depending on the Hamming code used), whereas CRC is a convolution code that works on data of any size. In this paper, the authors will show how CRC helps in removing errors by passing three distorted signals and using CRC to receive the signal error free in the MATLAB environment.

Sampling technique for noisy and borderline examples problem in imbalanced classification

Thermal errors are the major contributor to the dimensional errors of a workpiece in precision machining. Error compensation technique is a cost-effective way to reduce thermal errors. Accurate modeling of errors is a prerequisite of error compensation. In this paper, a thermal error model was proposed by using projection pursuit regression (PPR). The PPR method improves the prediction accuracy of thermal errors in the computer numerical control (CNC) turning center. A thermal error compensation system was developed based on the PPR model, and which has been applied to the CNC turning center in daily production. The results show that the thermal drift in workpiece diameter has been reduced from 34 to 5 μm.

With the continuous development of manufacturing industry, the application range of NC machining technology has been further expanded. The contour accuracy is strongly related to the NC machining quality as a key machine tool performance indicator. Its application efficiency is plainly low as the majority of offline compensation-based contour accuracy adjustments rely heavily on manual experience. Moreover, the isolated research on automatic error compensation and its combination with algorithms does not start with the characteristics of contour accuracy in data processing. Therefore, based on the advantages of strong the robustness of the fuzzy algorithm and the high effectiveness of parameter adjustment, an automatic compensation method for NC machining contour error based on fuzzy control is proposed. The contour error prediction model is designed according to the machining path, and then the automatic compensation strategy for contour error under fuzzy control is designed based on the feed speed. The results showed that under this method, the contour error can reach a maximum of 0.06 and a minimum of 0.025, which was 0.015 lower than the minimum contour error of genetic algorithm. This indicated that the method greatly reduced the CNC machining contour error and improved the contour accuracy, as well as reducing the time cost of contour error compensation, improving the efficiency of contour error compensation, and realizing the automation of error compensation control capability. This is helpful for advancing CNC machining automation technology and supporting the intelligent development of machinery manufacturing.

The increasing rate of transient faults necessitates the use of on-chip fault-tolerant techniques in embedded microprocessors. Performance overhead is a challenging problem in on-chip fault-tolerant techniques used in the random logic of the embedded microprocessors. This paper presents a signature-based error detection and roll-back recovery technique for the control logic with much lower performance overhead as compared to many previous techniques. The low performance overhead is achieved by eliminating the fault masking overhead cycles in the previous techniques. The performance overhead is analytically studied, and the analytical results recommend at which fault rate the use of the technique is preferred. To measure the cycle time of the pipeline critical path and area overhead, this technique has been implemented and synthesized using a behavioral VHDL model of the Leon2 processor. The synthesis results show that the area and the cycle time overhads of the technique are only 17.7% and 3.4%, respectively. In addition, the injection of about 74000 transient single bit-flip faults into the control logic part of the Leon2 processor shows that the technique detected about 99% of the injected faults.

Maintenance of beam alignment and centering in Antares requires error-detection techniques and appropriate correction methods via computer- controlled mirror positioners. A technique for error detection is presented as well as algorithms for simultaneous correction of both beam alignment and centering using optically coupled mirror sets.

The various codes are used for the error detection and correction in the field of communication. Some are for the single bit error and some are for the multiple bits error. Reed-Muller algorithm realizes the ability of multiple bits error detection and correction. With the superior error correction capability, these codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. Reed-Muller codes cover a wide range of service requirements and diverse interference conditions in wireless applications and can operate at both high and low code rates. In this paper, the comparison of Reed-Muller codes with different other codes for error detection and correction of multiple bits is proposed and further we can implement it on a Xilinx field programmable gate array (FPGA) device. Using Reed-Muller method the data is transferred from transmitter to receiver without any error. The error detection and correction principle and realization methods are described in detail. The multiple bits error detection and correction with Reed-Muller algorithm method can improve the bit error rate and packet error rate effectively.

Error detection and correction techniques are base for faultless data transmission. Hamming code is widely used technique for single bit error detection and correction. Aside from this, low power circuits are in a wide use too, as they can lead to many advantages like cost minimization, performance improvement, etc. Hamming distance-based error data detection and correction algorithm is presented, which has integrated low power XOR circuit. Experiments show, that by using proposed method, power consumption is being decreased by about $\sim 19$% compared with design with standard gates. However, as less low power gates are slower, delays in circuit has been increased by about $\sim 14 \%$.

The growth in mobile communication and Internet usage has lead to increase in demand for robust transmission of compressed video over error prone channels. The quality of decoded video in erroneous environments depends on efficient detection, localization and concealment of errors. In fact, the role of error detection and localization is very important because undetected erroneous macroblocks (MBs) are not concealed and correct MBs may be termed as erroneous. However, traditional error detection method isn't enough for detection. A novel detection method proposed recently can detect some special errors, but can't make precise localization. In this paper, an improved error detection and localization technique using syntactic, semantic and statistical information in MPEG-4 is proposed. This scheme can detect most types of transmission error and locate the exact position of the first error. Experimental results show the proposed technique can achieve high error detection ratio, usually more than 90%, and increase the decoded video quality efficiently

This paper presents an error compensated piecewise linear logarithmic arithmetic unit for Phong lighting hardware acceleration. Two novel error compensation techniques have been applied to differentiate finer bounds within piecewise linear (PWL) approximation intervals to achieve a lower absolute mean error rate with minimal increment in resource costs. Area/power/error performances of the logarithmic unit designs are presented for the proposed topologies applied to a five-interval base-2 PWL logarithm approximation circuit in comparison to its baseline counterpart. In addition, the design is applied to a single-cycle Phong lighting hardware accelerator and evaluated for graphical estimation accuracy at the system-level.

Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive adversaries with limited attack capabilities. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200%-400%). In this paper we propose a novel error detection technique based on the random selection of linear arithmetic codes and explore the use of this technique for the protection of the multiplier, which is a basic block in many public-key cryptographic devices. The error detection technique does not imply any limitations on the types of errors at the output of the device, e.g., the multiplicity of the error does not have to be small. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (at most 50% area overhead for the protection of multipliers) due to the fact that no nonlinear operations are needed for the encoder and decoder.

Signal processing comes with a wide range of applications that includes enhancement of signal quality to improve accuracy and selection of required component from a received signal. As technology advances, signal processing systems has become more complex in which filters may operate in parallel. In such complex systems, there is a necessity for an efficient error tolerant implementation as reliability becomes critical. In this paper, a technique for error detection and correction is proposed which can detect and correct two errors by using a section wise single error correcting approach and the technique is explained in two approaches. Both approaches of technique can be applied in a parallel FIR filter configuration where filters use same response for same or different input signals. Thus, system homogeneity plays an important role in proposed technique for error detection and correction.

Fault tolerance is of great importance for big data systems. Although several software-based application-level techniques exist for fault security in big data systems, there is a potential research space at the hardware level. Big data needs to be processed inexpensively and efficiently, for which traditional hardware architectures are, although adequate, not optimum for this purpose. In this paper, we propose a hardware-level fault tolerance scheme for big data and cloud computing that can be used with the existing software-level fault tolerance for improving the overall performance of the systems. The proposed scheme uses the concurrent error detection (CED) method to detect hardware-level faults, with the help of Scalable Error Detecting Codes (SEDC) and its checker. SEDC is an all unidirectional error detection (AUED) technique capable of detecting multiple unidirectional errors. The SEDC scheme exploits data segmentation and parallel encoding features for assigning code words. Consequently, the SEDC scheme can be scaled to any binary data length “n” with constant latency and less complexity, compared to other AUED schemes, hence making it a perfect candidate for use in big data processing hardware. We also present a novel area, delay, and power efficient, scalable fault secure checker design based on SEDC. In order to show the effectiveness of our scheme, we (1) compared the cost of hardware-based fault tolerance with an existing software-based fault tolerance technique used in HDFS and (2) compared the performance of the proposed checker in terms of area, speed, and power dissipation with the famous Berger code and m-out-of-2m code checkers. The experimental results show that (1) the proposed SEDC-based hardware-level fault tolerance scheme significantly reduces the average cost associated with software-based fault tolerance in a big data application, and (2) the proposed fault secure checker outperforms the state-of-the-art checkers in terms of area, delay, and power dissipation.