A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic

Successive generations of processors use smaller transistors in the quest to make more powerful computing systems. It has been previously studied that smaller transistors make processors more susceptible to soft errors (transient faults caused by high energy particle strikes). Such errors can result in unexpected behavior and incorrect results. With smaller and cheaper transistors becoming pervasive in mainstream computing, it is necessary to protect these devices against soft errors; an increasing rate of faults necessitates the protection of applications running on commodity processors against soft errors. The existing methods of protecting against such faults generally have high area or performance overheads and thus are not directly applicable in the embedded design space. In order to protect against soft errors, the detection of these errors is a necessary first step so that a recovery can be triggered.

Successive generations of processors use smaller transistors in the quest to make more powerful computing systems. It has been previously studied that smaller transistors make processors more susceptible to soft errors (transient faults caused by high energy particle strikes). Such errors can result in unexpected behavior and incorrect results. With smaller and cheaper transistors becoming pervasive in mainstream computing, it is necessary to protect these devices against soft errors; an increasing rate of faults necessitates the protection of applications running on commodity processors against soft errors. The existing methods of protecting against such faults generally have high area or performance overheads and thus are not directly applicable in the embedded design space. In order to protect against soft errors, the detection of these errors is a necessary first step so that a recovery can be triggered. To solve the problem of detecting soft errors cheaply, we propose a profiling-based software-only application analysis and transformation solution. The goal is to develop a low cost solution which can be deployed for off-the-shelf embedded processors. The solution works by intelligently duplicating instructions that are likely to affect the program output, and comparing results between original and duplicated instructions. The intelligence of our solution is garnered through the use of control flow, memory dependence, and value profiling to understand and exploit the common-case behavior of applications. Our solution is able to achieve 92% fault coverage with a 20% instruction overhead. This represents a 41% lower performance overhead than the best prior approaches with approximately the same fault coverage.

Among hardware-level techniques for fault and error detection, the Body Built-In Current Sensors (BBICS) offer a compact and effective alternative for detecting single, short-duration, long-duration, and multiple (and simultaneous) transient faults. This kind of sensor combines the high fault detection effectiveness of costly fault-tolerance schemes (e.g. duplication with comparison) with the low-area and low-power overheads of less effective mitigation techniques such as time redundancy approaches. In addition, these sensors are perfectly suitable for IC system design flows based on CMOS standard cells of commercial libraries. This chapter firstly presents the fundamentals and the history of built-in current sensors, after it classifies and describes the different state-of-the-art BBICS architectures. Moreover, this chapter defines what we call as the reference sensitivity of a sensor (or a memory element) in detecting single transient faults, and it compare state-of-the-art BBICS architectures in terms of their sensitivity in detecting transient faults and area overhead.

The incorporation of error detection and recovery mechanisms becomes mandatory as the probability of the occurrence of transient faults increases. The detection of control flow errors has been extensively investigated in literature. However, only few works have been conducted towards recovery from control-flow errors. Generally, a program is re-executed after error detection. Although re-execution prevents faults from corrupting data, it does not allow the application to run to completion correctly in the presence of an error. Moreover, the overhead of re-execution increases prominently. The current study presents a pure-software method based on encoded signatures to recover from control-flow errors. Unlike general signature monitoring techniques, the proposed method targets not only interblock transitions, but also intrablock and inter-function transitions. After detecting the illegal transition, the program flow transfers back to the block where the error occurred, and the data errors caused by the error propagation are recovered. Fault injection and performance overhead experiments are performed to evaluate the proposed method. The experimental results show that most control flow errors can be recovered with relatively low performance overhead.

Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive adversaries with limited attack capabilities. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200%-400%). In this paper we propose a novel error detection technique based on the random selection of linear arithmetic codes and explore the use of this technique for the protection of the multiplier, which is a basic block in many public-key cryptographic devices. The error detection technique does not imply any limitations on the types of errors at the output of the device, e.g., the multiplicity of the error does not have to be small. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (at most 50% area overhead for the protection of multipliers) due to the fact that no nonlinear operations are needed for the encoder and decoder.

In space radiation environment, a large number of cosmic ray often results in transient faults on on-board computer. These transient faults lead to data flow errors or control flow errors during program running. For the control flow errors caused by transient faults, this paper proposes a control flow checking method based on classifying basic blocks CFCCB. CFCCB firstly classifies the basic blocks based on the control flow graph that has been inserted the abstract blocks. CFCCB then designs formatted signatures for the basic blocks and inserts the instructions for comparing and update signatures into every basic block for the purpose of checking the control flow errors that are inter-blocks, intra-blocks or inter-procedures. Compared to existing algorithms, CFCCB not only has high label express ability, but also can be configured flexibly. The fault injection experiment results of CFCCB and other similar algorithms have shown that, the average fail rate of programs with CFCCB has decreased to 19.9% at the cost of increasing the executing time by 34% and increasing the memory overhead by 41.5% in average. CFCCB has lower performance and memory overhead, and has highest reliability among the similar algorithms.

Error detection is a fundamental need in most computer networks and communication systems in order to combat the effect of noise. Error detection techniques have also been incorporated with lossless data compression algorithms for transmission across communication networks. In this paper, we propose to incorporate a novel error detection scheme into a Shannon optimal lossless data compression algorithm known as Generalized Luröth Series (GLS) coding. GLS-coding is a generalization of the popular Arithmetic Coding which is an integral part of the JPEG2000 standard for still image compression. GLS-coding encodes the input message as a symbolic sequence on an appropriate 1D chaotic map Generalized Luröth Series (GLS) and the compressed file is obtained as the initial value by iterating backwards on the map. However, in the presence of noise, even small errors in the compressed file leads to catastrophic decoding errors owing to sensitive dependence on initial values, the hallmark of deterministic chaos. In this paper, we first show that repetition codes, the oldest and the most basic error correction and detection codes in literature, actually lie on a Cantor set with a fractal dimension of }{} frac{1}{n} , which is also the rate of the code. Inspired by this, we incorporate error detection capability to GLS-coding by ensuring that the compressed file (initial value on the chaotic map) lies on a Cantor set. Even a 1-bit error in the initial value will throw it outside the Cantor set, which can be detected while decoding. The rate of the code can be adjusted by the fractal dimension of the Cantor set, thereby controlling the error detection performance.

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Concurrent Error Detection (CED) techniques based on hardware duplication are widely used to enhance system dependability. All CED techniques contain some form of redundancy. In this paper we present simulation results to quantitatively compare various CED schemes based on their area overhead and protection (data integrity) they provide against multiple failures. We describe some studies of parity based concurrent error detection in S-boxes. In this work substitution blocks of PP-1 block-cipher, designed for platforms with very limited resources (for example for embedded systems), are used as a case study.

In computer communication and telecommunication applications, error detection and correction techniques must be employed to ensure a reliable data transmission from the source to the destination. Two of the most prevailing techniques, Cyclic Redundancy Check (CRC) detection and Hamming code correction, are implemented and analyzed. The CRC method picks up prominence because it joins three focal points: extraordinary blunder identification capacities, minimal overhead, and simplicity of usage. Moreover, both the CRC and Hamming code are binary linear codes. However, one significant difference is that Hamming code only works on data of some fixed size (depending on the Hamming code used), whereas CRC is a convolution code that works on data of any size. In this paper, the authors will show how CRC helps in removing errors by passing three distorted signals and using CRC to receive the signal error free in the MATLAB environment.

Sampling technique for noisy and borderline examples problem in imbalanced classification

Log-based recovery and replay systems are important for system reliability, debugging and postmortem analysis/recovery of malware attacks. These systems must incur low space and performance overhead, provide full-system replay capabilities, and be resilient against attacks. Previous approaches fail to meet these requirements: they replay only a single process, or require changes in the host and guest OS, or do not have a fully-implemented replay component. This paper studies full-system replay for uniprocessors by logging and replaying architectural events. To limit the amount of logged information, we identify architectural nondeterministic events, and encode them compactly. Here we present ExecRecorder, a full-system, VM-based, log and replay framework for post-attack analysis and recovery. ExecRecorder can replay the execution of an entire system by checkpointing the system state and logging architectural nondeterministic events, and imposes low performance overhead (less than 4% on average). In our evaluation its log files grow at about 5.4 GB/hour (arithmetic mean). Thus it is practical to log on the order of hours or days between checkpoints. It can also be integrated naturally with an IDS and a post-attack analysis tool for intrusion analysis and recovery.

In this paper we present a zero-performance-overhead online fault detection and diagnosis scheme that exploits the vertical proximity of hardware inherent in 3D stacked integrated circuits (3D-SIC). We consider a 3D stacked processor executing independent instruction streams from different threads, on each die. We propose the vertical clustering of functionally identical computational blocks in order to enable the utilization of the 3D specific low-latency interlayer communication infrastructure. The clustering facilitates the parallel re-execution of instructions on idle units located in the proximity of the units which initially computed them and in this way creates the means for fault diagnosis and detection. We detail the control, interconnection communication infrastructure, instruction distribution, and results processing policies required for our scheme. To determine the effectiveness of the approach, we evaluate its performance in terms of diagnosis latency and percentage of verified operations on 3 to 8 core processors implemented on 3 to 8 tier 3D-SICs, respectively, by means of simulations. Our experiments indicate that the diagnosis latency ranges from 9 to 5 cycles, for 3 to 8 cores, respectively. For transient fault detection our simulations indicate that 86% to 94% of all executed instructions are verified, for 3 to 8 cores, respectively. When only one of the layers is protected against transient faults the number of verified operations increases to 94% to 99%, for the same simulation conditions. This suggests that, if certain conditions are fulfilled at design time, our approach can completely protect one instruction stream identified as being critical for the application. Our simulations clearly indicate that the proposed scheme has the potential to improve the 3D stacked integrated circuits dependability with no performance overhead and at the expense of little area overhead.

The advent of in-memory computing has introduced a new paradigm of computation, which offers significant improvements in terms of latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect of the hardware variations and non-idealities of the emerging memory technologies may significantly compromise the accuracy of inferred neural networks and result in malfunctions in safety-critical applications. This article addresses the issue from three different perspectives. First, we describe the technology-related sources of these variations. Then, we propose an architectural-level mitigation strategy that involves the coordinated action of two checksum codes designed to detect and correct errors at runtime. Finally, we optimize the area and latency overhead of the proposed solution by using two accuracy-aware hardware-software co-design techniques. The results demonstrate higher efficiency in mitigating the accuracy degradation of multiple AI algorithms in the context of different technologies compared with state-of-the-art solutions and traditional techniques such as triple modular redundancy. Several configurations of our implementation recover more than 95% of the original accuracy with less than 40% of the area and less than 30% of latency overhead.This article is part of the themed issue 'Emerging technologies for future secure computing platforms'.

The use of automatic error detection and compensation techniques for testing the class cBigNumber written in C++ is discussed; this class is designed for performing operations on unbounded integer numbers. It implements the standard operations of C++, square rooting, binary exponentiation, and Miller-Rabin primality test. The class is tested in the automatic mode. The reliability of computations is ensured using the built-in error control and compensation tools.