Threading Dislocations in InGaAs/GaAs (001) Buffer Layers for Metamorphic High Electron Mobility Transistors

Metamorphic semiconductor devices such as high electron mobility transistors (HEMTs), light-emitting diodes (LEDs), laser diodes, and solar cells are grown on mismatched substrates and typically exhibit a high degree of lattice relaxation. Linearly-graded buffer layers are commonly used to accommodate the lattice mismatch in these structures, but theoretical and experimental studies suggest that non-linear compositional grading might allow lower threading dislocation densities and improved device performance. In this work we have compared the threading dislocation densities in heterostructures employing bi-parabolic, linear, and S-graded (complementary error function) buffer layers. The threading dislocation densities were calculated using the approximate Matthews, Mader, and Light model (1) for plastic flow and by assuming that the coefficient for second-order annihilation and coalescence reactions between threading dislocations is equal to the length of misfit dislocations.

ABSTRACTMethods for forming Ge epitaxial layer on Si (100) substrate have been vigorously sought due to potential applications of such structure as a virtual substrate for III-V devices on Si. Various methods were proposed to realize low threading dislocation density and smooth surface. To date, such methods involve more than one of thick (micrometer order) SiGe buffer growth process, high temperature annealing steps and CMP process, which could compromise reliability and suitability for production.In this study, we report feasibility of a thin (in the order of 10nm) SiGe buffer layer to realize pure Ge epitaxial layer with good crystalinity, low threading dislocation density, and smooth surface without high temperature annealing steps and CMP process.As a result, we achieved shorter time for growth of practical thickness of crystalline Ge on Si (100) substrate, and also get the high quality Ge epitaxial layer which has low threading dislocation density with very smooth surface.Ge epitaxial layer and underlying thin SixGe1−x buffer layer were grown on Si (100) substrate using a cold wall UHV-CVD system. Source gases of Si and Ge were Si2H6 and GeH4, respectively. No carrier gas was used for this process. SiGe buffer layer was grown on Si(100) substrate at 450 – 520˚C. Two-step growth process was employed to grow Ge epitaxial layer on the buffer layer. Ge seed layer was grown at a low temperature (350–400˚C), followed by Ge thick layer growth at a high temperature (550–650˚C). XRD, TEM, EPD, and AFM were used for characterization of Ge epitaxial layer.Optimization of growth temperature and source gas flow rate ratio enabled to obtain an effective buffer layer thinner than 10nm. The thin buffer layer realizes process time shortening, which is within 10min, and the smooth surface is realized without crosshatch structure. The buffer thickness is 1/160 to 1/1000 than that of previously known methods using thick SiGe buffer layers. Thin SiGe buffer also enabled process time shortening for Ge seed layer growth as two-dimensional Ge layer was formed faster on the thin SiGe buffer layer than on Si. XRD of the Ge seed layer showed 97% relaxation as grown and fully relaxed at 550˚C. The threading dislocation density of the top Ge layer was estimated below 1E7counts/cm2 by TEM and EPD.The misfit dislocations oriented along [110] at the interface between the SiGe buffer layer and the Ge layer and the distances are 9.5nm constantly in cross-sectional TEM image. We are checking the surface roughness of the Ge epitaxial layer by using AFM.

p-type Ge channel modulation doped heterostructures with very high room-temperature mobilities

We have grown blue light-emitting diodes (LEDs) with low threading dislocation densities (TDDs) by using SiN interlayers on Si (111) substrates. Our growth technique using SiN layers makes it possible to decrease twist components (edge-type threading dislocation components). The edge-type TDDs are almost the same values as those of LEDs grown on Al₂O₃ (0001) substrates. EQE of LEDs grown on Si (111) substrates increases with decreasing edge-type dislocation in the low-current-density region, and the EQE of the sample with low TDD is almost as high as that of the LED grown on an Al₂O₃ (0001) substrate at room temperature. It is found that the hot/cold factors (HCFs) of LEDs grown on Si (111) substrates increase with decreasing edge-type dislocations in the low-current-density region, but are less than those of an LED grown on an Al₂O₃ (0001) substrate. Time-resolved photoluminescence (TRPL) shows that the dominant origin of the thermal quenching is edge-type dislocations in our samples, but other defects such as screw-type dislocations also contribute to it. We also found the fluctuated emission patterns consisting of bright and dark areas originated from the difference of Shockley–Read–Hall (SRH) type defect densities in the multi-quantum wells (MQWs) grown on Si (111) substrates. The bright areas spread, and the configurations of the bright areas change into ring-like patterns with reducing edge-type TDDs. We suggest that the internal quantum efficiency (IQE) of dark areas should be promoted to improve the performance of the MQWs grown on Si (111) substrates.

Interfacial engineering for semi-insulating GaN/sapphire template with low dislocation density

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si 0.8Ge 0.2 pseudo-substrates

Line, point and surface defect morphology of graded, relaxed GeSi alloys on Si substrates

Evolution of threading dislocations in MOCVD-grown GaN films on (1 1 1) Si substrates

ABSTRACTWe have grown linearly compositionally graded GexSi1−x structures at high temperatures (700–900°C) on Si substrates to form a surface which resembles a GexSi1−x substrate. We have obtained completely relaxed structures with x≤0.50 and threading dislocation densities in the 105cm−2 - 106cm−2 range. Because of the very low threading dislocation densities, the structures appear dislocation free in conventional transmission electron microscopy (TEM) cross-section and plan view. Employing the electron beam induced current technique (EBIC), we were able to consistently measure these low threading dislocation densities. A direct comparison of two x=0.35 films, one graded in Ge content and one uniform in Ge content, shows that compositional grading decreases the dislocation density by a factor of 100–1000. These. higher quality graded buffers have been used as templates for the subsequent growth of InGaP light emitting diodes (LED) and GexSi1−x/Si two-dimensional electron gas (2DEG) structures. Room temperature operation of orange-red LEDs were obtained at current densities of =600A/cm, and mobilities as high as 96,000 cm2/V-s were achieved at 4.2K in the 2DEG structures.

A method to grow a relaxed Si0.5Ge0.5 graded layer with a very smooth surface and a very low threading dislocation density using solid-source molecular-beam epitaxy is reported. This method included the use of Sb as a surfactant for the growth of a 2 μm compositionally graded SiGe buffer with the Ge concentration linearly graded from 0% to 50% followed by a 0.3 μm constant Si0.5Ge0.5 layer. The substrate temperature was kept at 510 °C during the growth. Both Raman scattering and x-ray diffraction were used to determine the Ge mole fraction and the degree of strain relaxation. Both x-ray reflectivity and atomic force microscopy measurements show a surface root mean square roughness of only 20 Å. The threading dislocation density was determined to be as low as 1.5×104 cm−2 as obtained by the Schimmel etch method. This study shows that the use of a Sb surfactant and low temperature growth is an effective method to fabricate high-quality graded buffer layers.

The understanding of lattice relaxation and dislocation dynamics in lattice-mismatched semiconductors makes it possible to design metamorphic device structures utilizing the dislocation compensation mechanism for reduced defects, improved performance, and enhanced reliability. We have developed a dislocation dynamics model accounting for misfit–threading interactions and have applied it to ZnSySe1−y/GaAs (001) heterostructures.1 Dislocation compensation involves the removal of threading dislocations associated with one sense of misfit dislocations by bending them over to create misfit dislocations of the opposite sense at an intentionally mismatched interface. Here we investigated the design of dislocation-compensated ZnSySe1−y/GaAs (001) heterostructures and considered the sulfur mole fraction tolerances applicable to such structures. We considered two types of structures: type A involved a uniform-composition (ungraded) layer on top of a uniform-composition buffer, while type B involved a uniform-composition layer on a linearly graded buffer. For each structure type we studied the requirements on the thickness and compositional profile of the buffer layer to optimize the removal of mobile threading dislocations from the top uniform (device) layer as well as the allowed tolerance in compositional overshoot to achieve structures with low threading dislocation density. We show for both types of structure that (i) for given compositional overshoot at the buffer–device layer interface, there is an optimum buffer thickness which minimizes the dislocation density; and (ii) for given buffer thickness there is an optimum overshoot which minimizes the dislocation density.

Heterogeneous material integration, especially for III-V semiconductors, has enabled more possibilities in designing optoelectronic and electronic devices, and the ability to exfoliate the bonded devices layers and reuse the expensive substrates makes it economically advantageous. In our case, we propose a method using easily fractured porous layer to transfer an InP thin film from an InP substrate to an alternate substrate; e.g., glass or a flexible structure such as PDMS. Here, we demonstrate the formation of such a porous InP layer which exhibits a surface that is nearly fully dense as well as the ability to grow InP overlayers with low (< 106 cm-2) threading dislocation density. Also, we were able to transfer large area (> 1 cm2) InP layers onto PDMS substrates and glass slides.In our studies on (001) InP, we have demonstrated that the pore formation can be controlled as a function of depth during electrochemical etching. For as-etched porous layers, AFM scans on a 40 X 40 μm2 area show the lowest surface r.m.s. less than 40 Å despite of the pore features. In order to achieve both high-quality epitaxial growth and facile layer fracture, a dual porous layer structure with a more porous (mechanically weaker) under-layer was designed and fabricated by either adjusting the etching current density or changing the switching electrolyte concentration. The structures were annealed to understand the morphological evolution of the pore structure and to test the structural stability under simulated epitaxial growth condition. Under N2-purged environments, we observed that the surface remains stable (no change in surface pore morphology) with even slight improvement on roughness up to 550 °C and the layer maintained its porous structure at 650 °C. Large voids were observed after annealing at the interface between the high porosity buried layer and substrate, which is consistent with the ease by which it is to remove top layers from the substrate after annealing. Epitaxial layers were grown about 2 μm thick on porous surfaces with different porosities and both a cross-section TEM sample and a plan-view sample (> 35 μm2) were used to characterize the epitaxial growth. Since no observable threading dislocations were found in the plan-view sample, it sets a limit on the threading dislocation density in the mid-106 cm-2 range.Samples with dual porous layers were bonded to flexible PDMS substrates and easily peeled off due to the fracture at the high porosity layer. Another set of samples were bonded to glass slides with epoxy glue and the fractured surface was characterized under SEM.

This thesis presents a systematic study of InAs quantum dot (QD) growth on Sibased substrates. Two Si-based platforms were studied, namely the graded Si 1-x Ge x /Si substrate which has a high threading dislocation density (~10 6 cm -2 ), and the germaniumon-insulator (GeOI) platform which has a lower threading dislocation density (<10 5 cm -2 ).

High-quality Ge epilayers on Si with low threading-dislocation densities were achieved by a two-step ultrahigh vacuum/chemical-vapor-deposition process followed by cyclic thermal annealing. On large Si wafers, Ge on Si with threading-dislocation density of 2.3×107 cm−2 was obtained. Combining selective area growth with cyclic thermal annealing produced an average threading-dislocation density of 2.3×106 cm−2.We also demonstrated small mesas of Ge on Si with no threading dislocations. The process described in this letter for making high-quality Ge on Si is uncomplicated and can be easily integrated with standard Si processes.

Relaxed GexSi1−x epilayers with high Ge fractions but low threading dislocation densities have been successfully grown on Si (001) substrate by employing a stepped-up strategy and a set of low-temperature GeySi1−y buffers. We show that even if the Ge fraction rises up to 90%, the threading dislocation density can be kept lower than 5×106 cm−2 in the top layers, while the total thickness of the structure is no more than 1.7 μm.