High-quality Ge epilayers on Si with low threading-dislocation densities

High-quality Ge epilayers on Si with a low threading-dislocation density (TDD) were grown by a one step hot wire chemical vapor deposition process at 350°C without cyclic thermal annealing. The Ge layers with threading dislocation density (TDD) of 1-105 cm-2 for a 1.4 μm thick Ge layer were obtained on Si wafers of a diameter Ø = 5 cm. Root mean square of roughness (RMS) of ∼ 0.37 nm is achieved. The Ge layers produced are of high optical quality.

A GaAs quantum-well laser diode was directly grown on silicon (001) substrate by a hybrid technique comprising AlAs nucleation and thermal cycle annealing. The hybrid technique provided the advantages of superior surface roughness, high quantum efficiency, and low threading dislocation density (TDD) of a thin buffer. The TDD was quantitatively characterized through the electron channeling contrast imaging method. Directly grown GaAs on Si exhibited a TDD of 5.45 × 107 /cm2 with small thickness of approximately 1.5 µm. The roughness and quantum efficiency of GaAs on Si was enhanced by adopting the nucleation layer of AlAs. We found that there exists an optimal thickness of AlAs nucleation to be 1.68 nm through structural and optical analysis. Based on optimized GaAs on Si, the GaAs quantum-well laser diode was directly grown with a TDD of 2.5 × 107 /cm2. Whole epitaxial layers were grown by metalorganic chemical vapor deposition. An edge-emitting broad stripe laser diode was successfully fabricated with a cavity length and width of 1120 µm and 60 µm, respectively. The continuous-wave lasing at room temperature was realized with a threshold current density of 643 A/cm2 and maximum output power of 19.7 mW at a single facet, where a threshold current density of 317 A/cm2 was obtained under pulsed operation condition. This result would constitute a building block to realize silicon-based on-chip light sources.

A high-quality Ge epilayer on Si has emerged as a viable method to integrate III-V optoelectronics and to achieve high carrier mobility than conventional Si-based CMOS devices. The epilayer quality is often measured by the density of threading dislocations that adversely impact the carrier transport. A number of strategies have been developed in recent years to reduce the threading dislocation density in Ge epilayers grown on Si. These strategies include multiple post-growth annealing, liquid-phase epitaxy, epitaxial necking, and graded SiGe layers. In search of a relatively simple and low-temperature growth technique, we have previously demonstrated Ge "touchdown" on Si, where high-quality Ge is grown epitaxially on Si covered with a thin layer (~ 1.2 nm) of chemically grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Herein, we focus on the unique surface chemistry involving Ge, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and Si that gives rise to the formation of approximately 7-nm-wide windows in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer and selective growth of Ge on exposed Si rather than on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub>

We have grown blue light-emitting diodes (LEDs) with low threading dislocation densities (TDDs) by using SiN interlayers on Si (111) substrates. Our growth technique using SiN layers makes it possible to decrease twist components (edge-type threading dislocation components). The edge-type TDDs are almost the same values as those of LEDs grown on Al₂O₃ (0001) substrates. EQE of LEDs grown on Si (111) substrates increases with decreasing edge-type dislocation in the low-current-density region, and the EQE of the sample with low TDD is almost as high as that of the LED grown on an Al₂O₃ (0001) substrate at room temperature. It is found that the hot/cold factors (HCFs) of LEDs grown on Si (111) substrates increase with decreasing edge-type dislocations in the low-current-density region, but are less than those of an LED grown on an Al₂O₃ (0001) substrate. Time-resolved photoluminescence (TRPL) shows that the dominant origin of the thermal quenching is edge-type dislocations in our samples, but other defects such as screw-type dislocations also contribute to it. We also found the fluctuated emission patterns consisting of bright and dark areas originated from the difference of Shockley–Read–Hall (SRH) type defect densities in the multi-quantum wells (MQWs) grown on Si (111) substrates. The bright areas spread, and the configurations of the bright areas change into ring-like patterns with reducing edge-type TDDs. We suggest that the internal quantum efficiency (IQE) of dark areas should be promoted to improve the performance of the MQWs grown on Si (111) substrates.

In order to evaluate various buffer layers for metamorphic devices, threading dislocation densities have been calculated for uniform composition In x Ga1−xAs device layers deposited on GaAs (001) substrates with an intermediate graded buffer layer using the LMD model, where LMD is the average length of misfit dislocations. On this basis, we compare the relative effectiveness of buffer layers with linear, exponential, and S-graded compositional profiles. In the case of a 2 μm thick buffer layer linear grading results in higher threading dislocation densities in the device layer compared to either exponential or S-grading. When exponential grading is used, lower threading dislocation densities are obtained with a smaller length constant. In the S-graded case, lower threading dislocation densities result when a smaller standard deviation parameter is used. As the buffer layer thickness is decreased from 2 μm to 0.1 μm all of the above effects are diminished, and the absolute threading dislocation densities increase.

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si 0.8Ge 0.2 pseudo-substrates

Line, point and surface defect morphology of graded, relaxed GeSi alloys on Si substrates

Low threading dislocation Ge on Si by combining deposition and etching

Metamorphic semiconductor devices such as high electron mobility transistors (HEMTs), light-emitting diodes (LEDs), laser diodes, and solar cells are grown on mismatched substrates and typically exhibit a high degree of lattice relaxation. Linearly-graded buffer layers are commonly used to accommodate the lattice mismatch in these structures, but theoretical and experimental studies suggest that non-linear compositional grading might allow lower threading dislocation densities and improved device performance. In this work we have compared the threading dislocation densities in heterostructures employing bi-parabolic, linear, and S-graded (complementary error function) buffer layers. The threading dislocation densities were calculated using the approximate Matthews, Mader, and Light model (1) for plastic flow and by assuming that the coefficient for second-order annihilation and coalescence reactions between threading dislocations is equal to the length of misfit dislocations.

A method to grow a relaxed Si0.5Ge0.5 graded layer with a very smooth surface and a very low threading dislocation density using solid-source molecular-beam epitaxy is reported. This method included the use of Sb as a surfactant for the growth of a 2 μm compositionally graded SiGe buffer with the Ge concentration linearly graded from 0% to 50% followed by a 0.3 μm constant Si0.5Ge0.5 layer. The substrate temperature was kept at 510 °C during the growth. Both Raman scattering and x-ray diffraction were used to determine the Ge mole fraction and the degree of strain relaxation. Both x-ray reflectivity and atomic force microscopy measurements show a surface root mean square roughness of only 20 Å. The threading dislocation density was determined to be as low as 1.5×104 cm−2 as obtained by the Schimmel etch method. This study shows that the use of a Sb surfactant and low temperature growth is an effective method to fabricate high-quality graded buffer layers.

Characteristics comparison between GaN epilayers grown on patterned and unpatterned sapphire substrate (0 0 0 1)

Heterogeneous material integration, especially for III-V semiconductors, has enabled more possibilities in designing optoelectronic and electronic devices, and the ability to exfoliate the bonded devices layers and reuse the expensive substrates makes it economically advantageous. In our case, we propose a method using easily fractured porous layer to transfer an InP thin film from an InP substrate to an alternate substrate; e.g., glass or a flexible structure such as PDMS. Here, we demonstrate the formation of such a porous InP layer which exhibits a surface that is nearly fully dense as well as the ability to grow InP overlayers with low (< 106 cm-2) threading dislocation density. Also, we were able to transfer large area (> 1 cm2) InP layers onto PDMS substrates and glass slides.In our studies on (001) InP, we have demonstrated that the pore formation can be controlled as a function of depth during electrochemical etching. For as-etched porous layers, AFM scans on a 40 X 40 μm2 area show the lowest surface r.m.s. less than 40 Å despite of the pore features. In order to achieve both high-quality epitaxial growth and facile layer fracture, a dual porous layer structure with a more porous (mechanically weaker) under-layer was designed and fabricated by either adjusting the etching current density or changing the switching electrolyte concentration. The structures were annealed to understand the morphological evolution of the pore structure and to test the structural stability under simulated epitaxial growth condition. Under N2-purged environments, we observed that the surface remains stable (no change in surface pore morphology) with even slight improvement on roughness up to 550 °C and the layer maintained its porous structure at 650 °C. Large voids were observed after annealing at the interface between the high porosity buried layer and substrate, which is consistent with the ease by which it is to remove top layers from the substrate after annealing. Epitaxial layers were grown about 2 μm thick on porous surfaces with different porosities and both a cross-section TEM sample and a plan-view sample (> 35 μm2) were used to characterize the epitaxial growth. Since no observable threading dislocations were found in the plan-view sample, it sets a limit on the threading dislocation density in the mid-106 cm-2 range.Samples with dual porous layers were bonded to flexible PDMS substrates and easily peeled off due to the fracture at the high porosity layer. Another set of samples were bonded to glass slides with epoxy glue and the fractured surface was characterized under SEM.

ABSTRACTMethods for forming Ge epitaxial layer on Si (100) substrate have been vigorously sought due to potential applications of such structure as a virtual substrate for III-V devices on Si. Various methods were proposed to realize low threading dislocation density and smooth surface. To date, such methods involve more than one of thick (micrometer order) SiGe buffer growth process, high temperature annealing steps and CMP process, which could compromise reliability and suitability for production.In this study, we report feasibility of a thin (in the order of 10nm) SiGe buffer layer to realize pure Ge epitaxial layer with good crystalinity, low threading dislocation density, and smooth surface without high temperature annealing steps and CMP process.As a result, we achieved shorter time for growth of practical thickness of crystalline Ge on Si (100) substrate, and also get the high quality Ge epitaxial layer which has low threading dislocation density with very smooth surface.Ge epitaxial layer and underlying thin SixGe1−x buffer layer were grown on Si (100) substrate using a cold wall UHV-CVD system. Source gases of Si and Ge were Si2H6 and GeH4, respectively. No carrier gas was used for this process. SiGe buffer layer was grown on Si(100) substrate at 450 – 520˚C. Two-step growth process was employed to grow Ge epitaxial layer on the buffer layer. Ge seed layer was grown at a low temperature (350–400˚C), followed by Ge thick layer growth at a high temperature (550–650˚C). XRD, TEM, EPD, and AFM were used for characterization of Ge epitaxial layer.Optimization of growth temperature and source gas flow rate ratio enabled to obtain an effective buffer layer thinner than 10nm. The thin buffer layer realizes process time shortening, which is within 10min, and the smooth surface is realized without crosshatch structure. The buffer thickness is 1/160 to 1/1000 than that of previously known methods using thick SiGe buffer layers. Thin SiGe buffer also enabled process time shortening for Ge seed layer growth as two-dimensional Ge layer was formed faster on the thin SiGe buffer layer than on Si. XRD of the Ge seed layer showed 97% relaxation as grown and fully relaxed at 550˚C. The threading dislocation density of the top Ge layer was estimated below 1E7counts/cm2 by TEM and EPD.The misfit dislocations oriented along [110] at the interface between the SiGe buffer layer and the Ge layer and the distances are 9.5nm constantly in cross-sectional TEM image. We are checking the surface roughness of the Ge epitaxial layer by using AFM.

Epitaxial lateral overgrowth (ELO) has been used to reduce threading dislocation (TD) densities in GaN. This paper reports transmission and scanning electron microscopy studies of TDs in GaN films grown by ELO on GaN nanocolumns produced either during growth by MBE (method 1), or by self‐organised patterning on a uniform layer grown by MOCVD (method 2). In method 1, isolated nanocolumns grew without TDs, but some TDs formed when nanocolumns coalesced. Although some of these TDs extended through the overlayer, extensive lateral migration of others, depending on the dislocation type, led to dislocation annihilation, lowering the overall TD density. In method 2, a similar process of lateral migration of TDs was observed during ELO, resulting in a continuous GaN overlayer with TD densities less than 108 cm–2. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

The radiation tolerance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on high quality, low threading dislocation density (TDD) ammonothermal GaN and hydride vapor phase epitaxy GaN substrates was studied and compared to the radiation response of devices on SiC substrates where the TDD is 104 times higher. Hall and transport measurements were performed as a function of 2 MeV proton fluence. The threading dislocation density had no effect on the radiation response. Comparing the results with published data reveals that almost all irradiated GaN-based HEMTs respond to radiation damage similarly regardless of differences in initial film quality, device structure, aluminum mole fraction, etc. AlGaAs/GaAs HEMTs are also shown to behave similarly but are around ten times more sensitive to radiation damage than GaN-based HEMTs. Known values of the displacement energy thresholds in GaN and GaAs are used to calculate that 36% fewer defects are created in GaN than in GaAs, which is too small to cause a 1000% difference in radiation sensitivity between GaN- and GaAs-based HEMTs. An alternative explanation is proposed in which the piezoelectric field at the AlGaN/GaN interface causes scattered carriers to be reinjected into the 2DEG channel, thereby mitigating some of the harmful radiation effects.