Three-dimensional (3D) monolithically integrated photodetector and WDM receiver based on bulk silicon wafer.

In this paper a novel microwave photonics beamformer device concept, for single side band (SSB) 40 GHz modulated signals, is presented. The proposed device comprises tunable lasers, flat-top arrayed waveguide gratings (AWG), a Mach Zender Modulator (MZM), an all-pass ring resonator and photodetectors. The device can be produced as a photonic integrated circuit. The signals from the lasers (one for each beamformer radiant element) are multiplexed by the first AWG, modulated, and passed through the all-pass ring resonator. The AWG channel spacing and the ring resonator Free Spectral Range (FSR) are both set to be equal to 100 GHz. The signal is demultiplexed by a second AWG and finally photodetected. By tuning each laser within its corresponding AWG passband, the phase difference between the optical carrier and the 40 GHz microwave modulated signal for each beamformer element can be controlled. The difference is determined by the phase response of the all-pass ring resonator. A critical part of the design is the alignment between the resonances of the ring resonator and both AWGs, but this can be alleviated by using a single AWG in fold-back configuration. The power provided to each beamformer element is different due to the intrinsic non-uniform losses of the AWGs and the ring resonators, but this can also be solved either by properly setting the lasers power, or by means of additional optical amplifiers. The presented analysis is independent of the integration technology. In Silicon photonics, the AWGs and ring resonator can be produced, while the (hybrid) integration of lasers, modulator, photodetectors (and eventually amplifiers) is a challenge. The device can be monolithically integrated on semi-insulating InP technology.

Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

Fourier methods are widely used in optical information processing for time domain waveform synthesis and detection. In such approaches an input pulse is spectrally decomposed and modulated by an appropriately designed spectral filter. In general, various ultrafast applications may need either generation or characterization of waveforms depending whether their frequency response is or is not known a priori. Ultrafast pulses prove useful in driving or probing such systems because their broad, deterministic complex spectral amplitude “sees” a large continuous portion of the system transfer function. Traditionally, space domain spectral decomposition is used to perform optical Fourier processing, where pairs of gratings and lenses are used to decompose the spectral content of the pulsed, optical waveforms. Liquid crystal and acousto-optic (AO) modulators provide a means for introduction of somewhat arbitrary system transfer functions. More recently, compact waveguide-based approaches have used arrayed waveguide gratings (AWGs) to perform an analogous spectral decomposition to those achieved with traditional, free-space coupled gratings. Information processing arrangements using the space domain for transverse spectral decomposition benefit from the maturity of such techniques, with respect to basic understanding, component quality, and the excellent phase control that free-space manipulations provide. Component insensitivity to optical power permits the shaping and detecting of high peak power pulses used to drive nonlinear optical systems. Furthermore, nonlinear optical elements can be introduced directly into these processors to provide unique ultrafast waveform synthesis capabilities with response times in the range of femtoseconds. Drawbacks to free-space approaches include scaling in volume to achieve large time bandwidth products (TBWPs) and limiting the temporal extent of waveforms coupled back into a single-mode fiber (SMF). The origin of this last restraint is the time∕space interrelation inherent in traditional pulse shaping devices. AWG approaches rely on complex waveguide elements to circumvent large processor volumes and time∕space coupling issues, but they too are practically limited by fabrication requirements. The number of resolvable spots in the output waveform for both Fourier synthesis and direct space-to-time AWG approaches is equal to the number of waveguide channels. An alternative approach to Fourier processing relying on a single transverse spatial mode can better integrate with fiber systems and photonic lightwave circuits and will scale in length only for the achievement of large TBWPs. Fiber-based and fiber-integrated processors can manipulate optical waveforms in the time domain exploiting chromatic dispersion for longitudinal spectral decomposition and applying to it Fourier synthesis techniques. Drawing on the identical mathematical treatments of diffraction in space and dispersion in time, an approximate Fourier transform (FT) of an incident optical signal is achieved via chromatic dispersion after reaching the so-called “far-field approximation.” With such an amount of dispersion, the temporal waveform closely resembles the spectrum. Such a waveform is called a longitudinal spectral decomposition wave (SDW). A time-variant element (e.g., modulator) filters this SDW. And it is possible to recompose the pulse waveform through propagation in a conjugate dispersion source matched (i.e., of opposite sign but equal magnitude) to the first dispersive element. The number of resolvable spots that such a processor offers relies on a suitable modulation scheme and the experimental ability to disperse a sub-picosecond pulse using second-order dispersion.

Using low-temperature plasma-enhanced chemical vapor deposition, a silica-based arrayed-waveguide grating (AWG) filter has been monolithically integrated with germanium photodiodes on a silicon-based photonic platform. All the outputs of a 16-channel AWG with 200- GHz spacing have been equipped with germanium photodiodes. All wavelength channels of the integrated device were confirmed to function as a wavelength-division-demultiplexing receiver for 1.25-Gbps PRBS signals. In addition, we have successfully mounted multi-channel transimpedance amplifiers and limiting amplifiers on the integrated photonic device using flipchip bonding technology.

Monolithic integration of an InP-based O-band 4-channel arrayed waveguide grating (AWG) to a uni-traveling carrier photodiode (UTC-PD) array is realized by the selective area growth (SAG) technique. The passive-active buttjoint design is introduced and experimentally proved to ensure both good compatibility between the PD fabrication process and the SAG technique, and high photodiode quantum efficiency under the complex butt-joint geometry. An extended coupling layer is adopted between the AWG output waveguides and the PD mesa. The extended coupling layer length, the regrowth boundary edge position and the AWG etching edge position relative to the heterogeneous butt-joint boundary, and the refractive indices of the PD collector and coupling layer are optically simulated and optimized by a finite-difference time-domain method. It is found that the extended coupling layer, compared with the un-extended situation, ensures a good matched optical field from AWG to PD and could reduce nearly 30% quantum efficiency loss when connecting seamlessly to the regrown InP AWG top cladding layer. A stable high efficiency around 80% is maintained within an extended layer length from 7.5 m to 15.0 m. The regrowth boundary edge into the coupling region will cause a drastic efficiency oscillation up to 20% period with the increase of distance. The efficiency drop is also attributed to the light scattering at the regrowth boundary edge, caused by the optical field mismatch, while the oscillation comes from the alternative light power concentration between the coupling layer and the core layer, for the light scattering is only obvious when the light power is well concentrated in the coupling layer. The AWG etching edge position deviation from the butt-joint boundary, however, exerts little influence on the PD quantum efficiency, which is believed not to bring obvious coupling loss during device fabrication. The higher UTC-PD collector refractive index is proved to be crucial for further better optical coupling from the coupling layer to the PD, with quantum efficiency rapidly increasing from around 0.1 to 0.8 when the index is increased from 3.20 to 3.42. By comparison, the efficiency is little affected by the coupling layer refractive index from 3.34 to 3.42.All things considered, we select a 10 m extended coupling layer, the refractive indices of both PD collector and the coupling layer to be 3.42, and align both the regrowth boundary edge and the AWG etching edge to the heterogeneous butt-joint boundary, and a PD quantum efficiency of 80% is expected. Owing to the extended coupling layer at the butt-joint, the SAG technique facilitates the PD fabrication process. The overgrown AWG top cladding layer ridge stretches out 4.67 m toward the PD, but not over the mesa yet, hence has little influence on the PD fabrication accuracy. The monolithic chip presents a uniform photodiode quantum efficiency of 76%, which accords well with theoretical value and confirms the butt-joint design. Central wavelengths for the four channels are 1347.0 nm, 1325.0 nm, 1308.0 nm, and 1286.5 nm, respectively. The low crosstalk level (below -22 dB) also indicates a good de-multiplexer performance.

A 16-channel 200 GHz arrayed-waveguide grating (AWG) (de)-multiplexer is demonstrated experimentally by utilizing Si3N4 buried optical waveguides, which have 50 nm-thick Si3N4 cores and a 15 μm-thick SiO2 cladding. The structure with an ultra-thin core layer helps to reduce the scattering due to the sidewall roughness and consequently shows very low loss of about 0.4~0.8 dB/m. When using this type of optical waveguide for an AWG (de)multiplexer, there is no problem associated with gap refill using the upper-cladding material even when choosing a small (e.g., 1.0 μm) gap between adjacent arrayed waveguides, which helps to reduce the transition loss between the FPR (free-propagation region) and the arrayed waveguides. Therefore, the demonstrated AWG (de)multiplexer based on the present Si3N4 buried optical waveguides has a low on-chip loss. The fabricated AWG (de)multiplexer is characterized in two wavelength ranges around 1310 nm and 1550 nm, respectively. It shows that the crosstalk from adjacent and non-adjacent channels are about -30 dB, and -40 dB, respectively, at the wavelength range of 1310 nm. The Si3N4 AWG (de)multiplexer has a temperature dependence of about 0.011 nm/°C, which is close to that of a pure SiO2 AWG device.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

We propose a tailored-waveguide based photonic chip with the functions of trapping, coherently manipulating, detecting and individually addressing an array of single neutral atoms. Such photonic chip consists of an array of independent functional units spaced by a few micrometers, each of which is comprised of one silica-on-silicon optical waveguide and one phase Fresnel microlens etched in the middle of the output interface of the optical waveguide. We fabricated a number of photonic chips with 7 functional units and measured optical characteristics of these chips. We further propose feasible schemes to realize the functions of such photonic chip. The photonic chip is stable, scalable and can be combined with other integrated devices, such as atom chips, and can be used in the future hybrid quantum system and photonic quantum devices.

Quantum biosensors offer a promising route to overcome the sensitivity and specificity limitations of conventional biosensing technologies. Their ability to detect biochemical signals at extremely low concentrations makes them strong candidates for next-generation sensing systems. This paper reviews the current state of quantum biosensors and discusses their future implementation in chip-scale platforms that combine microelectronic and photonic technologies. It covers key quantum biosensing approaches including quantum dots (QDs), and nitrogen-vacancy (NV) centers. This paper also considers their potential compatibility with electronic integrated circuits (EICs), photonic integrated circuits (PICs) and integrated quantum photonic (IQP) systems for future biosensing applications. To our knowledge, this is the first review to systematically connect quantum biosensing technologies with the development of microelectronic and photonic chip-based devices. The goal is to clarify the technological trajectory toward compact, scalable, and high-performance quantum biosensing systems.

Resistive random-access memory (RRAM) constitutes a promising technology for next-generation memory architectures due to its simple structure, high on/off ratio, and processing-in-memory ability. Its compatibility with emerging monolithic 3D (M3D) integration enables extremely high density using monolithic inter-tier vias (MIVs). However, both RRAM and M3D are susceptible to high defect rates due to immature manufacturing processes and process variations. Fault diagnosis for M3D-integrated RRAM and MIVs is therefore necessary to facilitate yield learning. In this work, we present a detailed characterization of RRAM faulty behaviors in the presence of process variations and manufacturing defects. We develop a diagnosis procedure by identifying appropriate reference resistance based on RRAM characteristics to efficiently distinguish fault origins. Results show that the proposed solution is compatible with existing test algorithms to significantly improve diagnostic resolution without affecting fault coverage.

We developed a low-polarization-dependent silica- based waveguide, which can be monolithically integrated with a silicon (Si) waveguide device on a silicon-on-insulator (SOI) substrate. For the monolithic integration, silica-based materials must be deposited at low temperature in order not to damage Si waveguide devices. Due to this low-temperature fabrication method, however, the silica films exhibit high residual stress, resulting in high material birefringence. In order to compensate for this birefringence, we introduce a multi-layer core structure. First, we design the structure taking the monolithic integration with the Si waveguide devices into account. Then, the designed waveguides and arrayed-waveguide gratings (AWGs) are fabricated using low-temperature fabrication processes. Next, we experimentally confirm that the waveguide exhibits low waveguide birefringence. In addition, we monolithically integrate the AWG and Si waveguide devices.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

Optical links and photonic integrated circuits require integration of photonic and electronic devices at chip, module, or board level. The complexity of such systems is motivating a need for system level CAD tools which can simulate electronic and photonic devices and circuits simultaneously and at multiple levels of abstraction. Furthermore integrating photonic devices into conventional electronic computer and communication systems needs to be justified in terms of cost, performance, and portability of existing computer software and hardware. Thus system level analysis of optoelectronic interconnect system is clearly necessary to ensure that an overall functional and performance requirements are met. The proposed approach for system level modeling is to integrate photonic device simulations into the established electronic design automation environment, particularly VHDL-based one. VHDL description of photonic devices will provide benefits such as portability of individual design, system level performance analysis before building a real system, and synthesis capability for a rapid- prototyping. This paper demonstrates the use of basic VHDL entities of various passive optical waveguide components and a special VHDL package (`Optical_Package') defining physical photonic parameters to verify the feasibility of this approach. It includes modeling and simulation of global signal distribution network on MCMs using optical interconnect and wavelength division (de)multiplexing-based optical link.

In this work, light and electric hybrid controlling optical phase shifters are proposed using an ionic‐gel polymer waveguide through the metal‐printing technique. The metal‐printing ionic‐gel polymer optical waveguide could generate conductive free ions by photothermal or electrothermal stimulation. Based on the ion relaxation dynamics of the gel polymer electrolytes, the multimode interference (MMI) type optical waveguide phase shifters controlled by external 360 nm pumping light and internal electrode heaters are designed and fabricated. The dynamic performances of the optical phase shifters are measured by light and electric hybrid tuning approaches. For near‐infrared C‐band signal wavelengths, the tuning efficiency of the optical phase shifters is obtained as 10.3 nm mW −1 using light driving and as 0.8 dB mW −1 through electric driving, respectively. The multi‐modal controlling technique is suitable for realizing a monolithic hybrid optical integrated system of photonic and electronic integrated circuits (ICs).

In this paper, a method to reduce arrayed waveguide path length increment (ΔL) by coupling to the slot array waveguide is proposed for the compact design of arrayed waveguide grating (AWG). This work effectively optimizes the design of layout to achieve better optoelectronic monolithic integration AWG. The corresponding coupling structure is also demonstrated. Finally, by using the slot waveguide, the layout of the AWG can be reduced to one third of the original size, and the bending loss is optimized. This method provides a feasible scheme for the design of optoelectronic integrated devices.