Three‐dimensional AND flash memory

The effect of a modified cell structure in the gate region on the electrical characteristics of three-dimensional (3D) NAND flash memory devices was investigated by using a technology computeraided design simulation. The interference in the memory devices induced by the pass voltage (Vpass) interference of 3D NAND flash was significantly affected depending on the cell size. The Vpass memory device with a modified cell structure was reduced due to an increase in the electron density of the inversion layer in comparison with conventional 3D flash memory devices, and their program operation was enhanced by the increased electric field. Furthermore, the program/erase margin of the proposed 3D NAND flash memory device was 15% larger than that of the conventional 3D NAND flash memory device.

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices.

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.

Three-dimensional (3D) flash memory is emerging as an attractive solution to overcome the scaling bottleneck in sub-20 nanometer design. Compared to the conventional planar flash memory, current 3D flash memory adopts charge-trap technology that can significantly enhance cell density and storage capacity. Despite these advantages, novel material and fabricate process in charge-trap flash memory bring new challenges. Recent studies demonstrate that charge-trap flash is sensitive to thermal yield. This issue does not happen in two-dimensional flash memory which adopts floating gate technology. For 3D flash memory with charge-trap technology, the high temperature will incur both charge loss and retention degradation. The large capacity data block in 3D flash memory also causes extra garbage collection overhead, which makes the temperature issue even worse. This paper presents TempLoad, a temperature-aware data allocation strategy for 3D charge-trap flash memory. TempLoad is a novel hardware and file system interface that can transparently allocate physical space based on the temperature status. TempLoad adopts several address mapping strategies to fully utilize the storage capacity and reduce the garbage collection overhead. The objective is to prevent the generation of hotspots and enhance the data integrity of 3D flash memory. Experimental results show that the proposed technique can reduce the peak temperature by 28.49% and reduce uncorrectable page errors by 83.71% with negligible timing overhead in comparison with previous work.

In this paper, an analytical model for finding the S‐factor of the FC‐SGT flash memory cell is derived. It is confirmed that the results of analysis agree well with the three‐dimensional simulation results. In comparison with the conventional planar flash memory cell, the FC‐SGT flash memory cell has a sufficiently smaller S‐factor. As a result, it is easier to realize multilevel operation by the FC‐SGT flash memory than by the conventional planar flash memory. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(8): 34–41, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20250

This paper proposes a new method to predict the data-retention time of long-term archive SSD with flexible-nLC NAND flash. This paper first reports that the conventional prediction overestimates the data lifetime based on the long-term data retention measurement. Then, a more precise prediction is proposed. By using this proposal, the most reliable and lowest cost memory architecture is determined. As a result, over 100-year data-retention is achieved, which is 25-times longer than the conventional TLC NAND flash memory.

In this article, we proposed a novel `I' shape floating gate applicable to the sub-70 nm flash memory cell with high performance and scalability. It has modified floating gate of conventional flash memory to have high coupling-ratio (CR), low effect of interference or cross-talk. Specifically, it has ∼13% higher CR and ∼33/46% lower effect of cross-talk of the bit-line/word-line state than those of conventional flash memory cell with scale-downed geometry. In addition, `I' shape flash memory cell shows improved characteristics about programming time, drain disturbance, read current, sub-threshold swing, and drain induced barrier lowering than conventional flash memory cell.

Recently, semiconductor companies such as Samsung, Hynix, and Micron, have focused on quad-level cell (QLC) NAND flash memory chips, because of the increase in the capacity of storage systems. The QLC NAND flash memory chip stores 4 bits per cell. A page in the QLC NAND flash memory consists of 16 sectors, which is two to four times larger than that of conventional triple-level cell flash NAND flash memory. Because of its large page size, when the QLC NAND flash memory is applied to the current storage system directly, each page space is not efficiently used, resulting in low space utilization in overall storage systems. To solve this problem, an efficient page collection scheme using cache for QLC NAND flash memory (PCS) is proposed. The main role of PCS is managing the data transmitted from the file system efficiently (according to the data pattern and size), and reducing the number of unnecessary write operations. The efficiency of PCS was evaluated using SNIA IOTTA NEXUS5 trace-driven simulation on QLC NAND flash memory. According to close observation, PCS significantly reduces 50% of write operations compared with previous page collection algorithms, by efficiently collecting the small data into a page. Furthermore, a cache idle-time determination algorithm is proposed to further increase the space utilization of each page, thereby reducing the overall number of write operations on the QLC flash memory.

With conventional nonvolatile flash memories approaching their scaling limit from cell-to-cell coupling and stress induced leakage current, many studies have been performed to explore the next generation memory technologies. Metal floating gate (FG) memory is one of the most promising candidates because of its less ballistic transport even with ultrathin floating gate (<10 nm). Enhancd memory performance including fast program speed, excellent data retention and program/erase (P/E) cycling endurance have been repored by P. Blomme et. al from IMEC. Moreover, S. Jayanti et. al explored that full Metal-FG could scaled down to even 1 nm thickness with excellent memory performance. Nevertheless, less attention had been paid on the study of tunneling layer which matches with full Metal-FG. Sufficient gate coupling ratio could obtained by using tunneling barrier without compromising the device performance. In our previous work , both the P/E speed and retention characteristic has been improved in the TaN floating gate flash memory based on the SiO2/HfO2 dual tunneling layer structure.The HfO2 layer adjacent to TaN was expected to suppress the inter-diffusion between tunneling dielectric and TaN FG. In this letter, bandgap engineered of the triple tunneling layer (SiO2/HfO2/Al2O3) has been demonstrated to be an effective method to optimize the performance of TaN Metal-FG. Compared to a device with a single SiO2 tunneling layer, faster program/erase speed and better data retention characteristics have been simultaneously achieved in this proposed structure. The schematic structure of a metal floating gate device is illustrated in Figure 1. P-type Si (100) wafers were cleaned by the standard Radio Corporation of America process. Devices with SiO2 (SiO2-4.5nm), SiO2/HfO2 (SiO2-2.7nm/HfO2-8nm) and SiO2/HfO2/Al2O3 (SiO2-2.7nm/HfO2-4nm/Al2O3-2nm) as tunneling layers are denoted as O-TaN , OH-TaN and OHA-TaN respectively. The thicknesses of tunneling layers were chosen for achieving the same effective oxide thickness (EOT). The memory characteristics such as operation speed and data retention were measured by using Agilent B1500A. The C-V hysteresis memory window of both O-TaN and OH-TaN device have been test. The improvement in the memory window for the OH-TaN device indicates the better carrier trapping capability of the stacked SiO2/HfO2 structure.It also can be attributed to the difference of the effective tunneling distance, which is resulted from the different potential drop when low-k and high-k dielectrics are employed as tunneling layer. Devices with SiO2/HfO2/Al2O3 (OHA) as tunneling layer was further characterized and compared with O-TaN and OH-TaN device. Compared to the O-TaN device, fast P/E speed along with large memory window is achieved with the OH-TaN and OHA-TaN device. Moreover, the device with OHA is slightly more advanced than the device with OH. The improvement of P/E speed in the OH-TaN and OHA-TaN structure can be explained by the energy band diagram under the program bias condition. Owing to the difference of voltage drop and bandgap between SiO2 and high-k (HfO2 and Al2O3), the effective tunneling distance is reduced in a high-k engineered tunneling layer structure. In addition, The reason that devices with OHA as tunneling layer shows slightly faster P/E speed than devices with OH as tunneling layer may attribute to a high defect state density at the interface of HfO2 and Al2O3. We also programmed the devices with an identical initial flat-band voltage to compare their room temperature retention characteristics. The OH-TaN and OHA-TaN structure exhibits negligible decrease in flatband voltage, whereas the control sample shows a significant loss of 2.7 V in flatband voltage in 104s. This can be attributed to the larger physical tunneling layer thicknesses of the engineered ones. The tunneling can be suppressed by large physical thickness under flat band or low electric field conditions. In this paper, a stacked high-k tunneling layer is proposed and investigated for TaN metal floating gate memory application. Compared to a single SiO2 tunneling layer, a stacked SiO2/HfO2 (SiO2-2.7nm/HfO2-8nm) and SiO2/HfO2/Al2O3 (SiO2-2.7nm/HfO2-4nm/Al2O3-2nm) tunneling layer structure have several memory performance improvements: a larger memory window, faster program/erase speed and better data retention characteristics. The improvement of P/E speed in the high-k tunneling barrier structure can be explained by the energy band diagram under the P/E bias condition. the effective tunneling distance is reduced Owing to the difference of voltage drop and bandgap between SiO2 and high-k (HfO2 and Al2O3). The performance enhancement of retention is attributed to the larger physical tunneling layer thicknesses of the high-k engineered ones. This work was supported by the National Natural Science Foundation of China (Grant No. 61306107, No. 61474137, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404). Figure 1

Three-dimensional (3D) stacking integration is offering many product benefits to SoC and memory: performance enhancements, product miniaturization and cost reduction. Besides, image sensors featuring 3D stacking of a specialized image sensor layer on the top of a deep submicron digital CMOS have just come to the market. The objective of this forum is to present applications and details of process integration, device techniques, circuits and system featuring 3D stacking integration. This will start with an overview of 3D stacking ICs, followed by a system perspective with scaling the memory wall. The next two talks will discuss challanges for power reduction with wide memory bandwidth, and performance gains through advanced packaging and chip stacking. This is followed by two talks covering challenges for foundry-specific issues and impact on device performance. The last two talks highlight how to integrate an imaging device on an SoC layer: technical issues and phenomenon of 3D stacked image sensor products, and evolution of 3D integration for imaging systems.

This paper reports a high-speed multilevel-cell nand Flash memory device using a Si- SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TiN- TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TaN (SOTTOT) engineered potential well (EW). The SOTTOT EW Flash memory device has very fast cell programming speed and good data retention. A 16-kbit nand memory block using SOTTOT cells was programmed using a forward-bias-adjusted programming scheme, which enables bit adjustability during page programming to suppress the development of fast bits. The SOTTOT memory block shows fast programming speed (~40 μs/page), tight threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) distribution (~0.22 V/level), and clear <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -level margins (~0.9 V) for the eight-level programming. The SOTTOT memory block also shows good resistance against pass/read disturbances as well as good ten-year data retention at an ambient temperature of 75 °C throughout 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> programming/erasing cycling.

When flash memory is used as a storage in embedded systems, block level translation layer is required between conventional filesystem and flash memory chips due to its physical characteristics. A far more efficient use of it is the design of a filesystem itself without no extra layer of translation. However, since flash filesystem does not use block device layer, it cannot utilize deferred I/O although deferred I/O enhances write latency by delaying the flushing jobs. Linux operating system generally uses the write back routine for deferred I/O using kernel thread, which writes back dirty pages and buffers through the block device layer. In this paper, we design and implement efficient I/O for JFFS2 flash filesystem based on flash memory. For this, we first analyze the write procedure of JFFS2 filesystem in detail, and derive the drawback and overhead. Then, we design the flash write back routine for deferred I/O. We apply it to the Linux JFFS2 by implementing fflush and flash_writeback kernel thread. The designed flash write back routine can reduce average write latency when the kernel buffers are enough to get the users data

Three-dimensional (3D) stacking technology enables integration of more memory on top of chip multiprocessors (CMPs). As the number of cores and the capacity of on-chip memory increase, the Non-Uniform Cache Architecture (NUCA) becomes more attractive. Compared to 2D cases, 3D stacking provides more options for the design of on-chip memory due to numerous advantages, such as the extra layout dimension, low latency across layers, etc. On the other hand, 3D stacking aggravates the thermal problem due to the increase of power density. In this work, we first study the design of 3D-stacked set-associative L2 caches through managing the placement of cache ways. The evaluation results show that the placement and corresponding management of 3D cache ways have an impact on the performance of CMPs. Then, we show that the efficiency of thermal control is also related to the placement of cache ways. For caches implemented with different memory technologies, the placement and management of cache ways have different effects on power consumption and power distribution. Consequently, we propose techniques to improve the efficiency of thermal control for different memory technologies. The evaluation results show the trade-off between performance and thermal control efficiency.

Cost evaluation on reuse of generic network service dies in three-dimensional integrated circuits

Conventional DRAM and flash memory are reaching their scaling limits thus motivating research in various emerging memory technologies as a potential replacement. Among these, phase change memory (PCM) has received considerable attention owing to its high scalability and multi-level cell (MLC) operation for high storage density. However, due to the resistance drift over time, the soft error rate in MLC PCM is high. Additionally, the iterative programming in MLC negatively impacts performance and cell endurance. The conventional methods to overcome the drift problem incur large overheads, impact memory lifetime and are inadequate in terms of acceptable soft error rate (SER). In this paper, we propose a new PCM memory architecture with heterogeneous PCM arrays to increase reliability, performance and lifetime. The basic storage unit in the proposed architecture consists of two single-level cells (SLCs) and one four-level cell (4LC). Using the reduced number of 4LCs compared to conventional homogeneous 4LC PCM arrays, the drift-induced error rate is considerably reduced. By alternating each cell operation between SLC and 4LC over time, the overall lifetime can also be significantly enhanced. The proposed architecture achieves up to 105 times lower soft error rate with considerably less ECC overhead. With simple ECC scheme, about 22% performance improvement is achieved and additionally, the overall lifetime is also enhanced by about 57%.