Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

In this article, we proposed a novel `I' shape floating gate applicable to the sub-70 nm flash memory cell with high performance and scalability. It has modified floating gate of conventional flash memory to have high coupling-ratio (CR), low effect of interference or cross-talk. Specifically, it has ∼13% higher CR and ∼33/46% lower effect of cross-talk of the bit-line/word-line state than those of conventional flash memory cell with scale-downed geometry. In addition, `I' shape flash memory cell shows improved characteristics about programming time, drain disturbance, read current, sub-threshold swing, and drain induced barrier lowering than conventional flash memory cell.

In this paper, an analytical model for finding the S‐factor of the FC‐SGT flash memory cell is derived. It is confirmed that the results of analysis agree well with the three‐dimensional simulation results. In comparison with the conventional planar flash memory cell, the FC‐SGT flash memory cell has a sufficiently smaller S‐factor. As a result, it is easier to realize multilevel operation by the FC‐SGT flash memory than by the conventional planar flash memory. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(8): 34–41, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20250

The effect of a modified cell structure in the gate region on the electrical characteristics of three-dimensional (3D) NAND flash memory devices was investigated by using a technology computeraided design simulation. The interference in the memory devices induced by the pass voltage (Vpass) interference of 3D NAND flash was significantly affected depending on the cell size. The Vpass memory device with a modified cell structure was reduced due to an increase in the electron density of the inversion layer in comparison with conventional 3D flash memory devices, and their program operation was enhanced by the increased electric field. Furthermore, the program/erase margin of the proposed 3D NAND flash memory device was 15% larger than that of the conventional 3D NAND flash memory device.

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices.

This paper proposes a new method to predict the data-retention time of long-term archive SSD with flexible-nLC NAND flash. This paper first reports that the conventional prediction overestimates the data lifetime based on the long-term data retention measurement. Then, a more precise prediction is proposed. By using this proposal, the most reliable and lowest cost memory architecture is determined. As a result, over 100-year data-retention is achieved, which is 25-times longer than the conventional TLC NAND flash memory.

Recently, semiconductor companies such as Samsung, Hynix, and Micron, have focused on quad-level cell (QLC) NAND flash memory chips, because of the increase in the capacity of storage systems. The QLC NAND flash memory chip stores 4 bits per cell. A page in the QLC NAND flash memory consists of 16 sectors, which is two to four times larger than that of conventional triple-level cell flash NAND flash memory. Because of its large page size, when the QLC NAND flash memory is applied to the current storage system directly, each page space is not efficiently used, resulting in low space utilization in overall storage systems. To solve this problem, an efficient page collection scheme using cache for QLC NAND flash memory (PCS) is proposed. The main role of PCS is managing the data transmitted from the file system efficiently (according to the data pattern and size), and reducing the number of unnecessary write operations. The efficiency of PCS was evaluated using SNIA IOTTA NEXUS5 trace-driven simulation on QLC NAND flash memory. According to close observation, PCS significantly reduces 50% of write operations compared with previous page collection algorithms, by efficiently collecting the small data into a page. Furthermore, a cache idle-time determination algorithm is proposed to further increase the space utilization of each page, thereby reducing the overall number of write operations on the QLC flash memory.

Three-dimensional (3D) flash memory is emerging as an attractive solution to overcome the scaling bottleneck in sub-20 nanometer design. Compared to the conventional planar flash memory, current 3D flash memory adopts charge-trap technology that can significantly enhance cell density and storage capacity. Despite these advantages, novel material and fabricate process in charge-trap flash memory bring new challenges. Recent studies demonstrate that charge-trap flash is sensitive to thermal yield. This issue does not happen in two-dimensional flash memory which adopts floating gate technology. For 3D flash memory with charge-trap technology, the high temperature will incur both charge loss and retention degradation. The large capacity data block in 3D flash memory also causes extra garbage collection overhead, which makes the temperature issue even worse. This paper presents TempLoad, a temperature-aware data allocation strategy for 3D charge-trap flash memory. TempLoad is a novel hardware and file system interface that can transparently allocate physical space based on the temperature status. TempLoad adopts several address mapping strategies to fully utilize the storage capacity and reduce the garbage collection overhead. The objective is to prevent the generation of hotspots and enhance the data integrity of 3D flash memory. Experimental results show that the proposed technique can reduce the peak temperature by 28.49% and reduce uncorrectable page errors by 83.71% with negligible timing overhead in comparison with previous work.

A new multitime programmable non-volatile memory cell using high voltage NMOS

High‐density and high‐speed charge‐trapping AND flash memory array is fabricated for the first time. A reliability of 10 4 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word‐lines, immunity to back‐pattern dependency, and fast bit‐sensing speed based on a parallel connected cell array structure, which are highly appropriate for three‐dimensional (3D) stacking. Finally, a novel 3D stacked vertical‐AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

We report reproducible multibit transparent flash memory in which a single solution-derived Ta2O5 layer is used simultaneously as a charge-trapping layer and a tunneling layer. This is different from conventional flash memory cells where two different dielectric layers are typically used. Under optimized programming/erasing operations, the memory device shows excellent programmable memory characteristics with a maximum memory window of ∼10.7 V. Moreover, the flash memory device shows a stable 2-bit memory performance and good reliability, including data retention for more than 104 s and endurance performance for more than 100 cycles. The use of a common charge-trapping and tunneling layer can simplify the fabrication of advanced flash memories.

3D NAND memory, featuring vertically stacked memory cells to enhance storage density and performance, serves as a critical component in modern data storage solutions and AI applications. In this paper, we investigated the electrical impact of memory hole (MH) mis-formation defects in a multi-tier three dimensional (3D) NAND memory technology. Despite being confined to local word lines (WLs) and source lines (SLs), such defects cause a global impact to all the memory cells in the same plane by slowing down their program speed. Specifically, the bit line potential of victim cells is disturbed when quick pass write (QPW) program technique is implemented. Such disturb originates from the interaction between source line and global bit line through the aggressor memory cells. Based on the failure mechanism, several approaches were proposed to improve the screen efficiency for these defects, which could otherwise become latent system failures.

When flash memory is used as a storage in embedded systems, block level translation layer is required between conventional filesystem and flash memory chips due to its physical characteristics. A far more efficient use of it is the design of a filesystem itself without no extra layer of translation. However, since flash filesystem does not use block device layer, it cannot utilize deferred I/O although deferred I/O enhances write latency by delaying the flushing jobs. Linux operating system generally uses the write back routine for deferred I/O using kernel thread, which writes back dirty pages and buffers through the block device layer. In this paper, we design and implement efficient I/O for JFFS2 flash filesystem based on flash memory. For this, we first analyze the write procedure of JFFS2 filesystem in detail, and derive the drawback and overhead. Then, we design the flash write back routine for deferred I/O. We apply it to the Linux JFFS2 by implementing fflush and flash_writeback kernel thread. The designed flash write back routine can reduce average write latency when the kernel buffers are enough to get the users data

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Organic nonvolatile memory has been considered a low-cost memory technology for flexible electronics and Internet-of-things (IoT). However, a major concern is the nonuniformity of memory units, which is primarily caused by random grain boundaries, interface defects, and charge traps, making it difficult to develop high-density reliable memory arrays. This nonuniformity problem would induce read error, which is directly caused by the narrow distribution margin of memory states and low noise tolerance in conventional organic memory cells. To break this limitation, a novel 2T memory cell employing a NOT-gate-like architecture achieving self-enhancing noise tolerance is presented. This unique cell consists of a pair of commonly-gated memory transistors with contradictory "write-and-erase" features. It functions as a voltage divider, producing a well-distinguished binary voltage output capability. The concept and design model of this brand-new 2T memory cell is thoroughly discussed. It is originally characterized by noise-tolerant memory cells irrespective of device nonuniformity. The noise tolerance range of this 2T memory cell is also investigated. The binary voltage-readable memory state with a large noise tolerance range is obtained. Moreover, the conceptual design of the 1T2T FeRAM cell is further developed for low-cost voltage-readable memory technology in wearable electronic applications.

With the rapid development of computer technology as a whole, the performance requirements of modern computer systems for storage technology are becoming higher and higher. This paper discusses the response to the problems that have arisen with the traditional storage in today's era, that is, the construction principle of the new storage three-dimensional memory (3D NAND) and the future development. Traditional storage in order to enhance the storage space of the plane flash memory, can only be components for shrinking, when shrinking to a certain extent when the flash memory will occur uncontrollable hidden danger, so the invention of 3D NAND. By vertically stacking many layers of memory cells, the storage density per unit area is greatly increased, with high-speed reading and writing, large capacity, low power consumption and other characteristics. Nowadays, 3D NAND is widely used in enterprises, and the industry is hopeful about the long-term prospects of the growing global demand for data generation and storage and the introduction of new technologies. The development of 3D NAND technology provides higher storage density and lower cost for NAND flash memory to meet the growing demand for data storage. This paper provides a systematic summary of existing research on 3D NAND in the hope that it will better enhance the overall technology improvement in the storage industry.