Three-dimensional simulation studies on electrostatic predictions for carbon nanotube field effect transistors

We have studied the effects of underlap's length and doping on the cutoff frequency, switching delay and on/off ratio of carbon nanotube field effect transistors (CNTFETs). We have proposed underlaps with different lengths, doping levels and doping profiles. Intrinsic and fringing field capacitances, transconductance, cutoff frequency, switching time and on/off ratio have been calculated for different CNTFET designs. Proposed CNTFETs have been simulated using nonequilibrium Green's function (NEGF) method. The gate capacitance has been calculated based on the charge on the gate contact according to Gauss law. Linear, uniform-light and two types of Gaussian dopant distributions have been studied. All the proposed devices improved the figures of merit. The charge density and the electric field under the gate are responsible for limiting the cutoff frequency. Our proposed underlaps with linear and uniform light doping have improved both switching delay and cutoff frequency. We have found that CNTFETs with longer underlaps and lighter doping have superior performance.

As aggressive scaling of conventional MOSFETs channel length reduces below 100 nm and gate oxide thickness below 3nm to improved performance and packing density. Due to this scaling short channel effects (SCEs) like threshold voltage roll-off & gate leakage current play a major role in determining the performance of scaled devices. The double gate (DG) MOSFETs are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. In recent years, nanotechnology has achieved significant progress in fabrication of various devices at nanometer like molecular diodes and Carbon Nanotube field effect transistors (CNFETs). This has provided new opportunities for VLSI circuits to achieve continuing cost minimization and performance improvement in a post-silicon-based-CMOS-technology era. Carbon Nanotube based FET devices are getting more and more importance today due to improved I-V characteristics and high channel mobility are considered as a replacement for future semiconductor devices.This paper presents design of DG MOSFET and DG CNFET by changing material like polysilicon with carbon nanotube at 20 nm technology. Simulation work on both devices has been carried out and presented in paper. Comparative study had been carried out for threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> & I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current. It observed that DG CNFET has good control on leakage current &ratio I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of DG-CNFET is 6.05 times greater than the DG-MOSFET.

In this paper, we investigate the effect of vacancy defects in carbon nanotube field effect transistor (CNTFET) by applying the self-consistent solution of the Schrodinger and Poisson equations within the non-equilibrium Green’s function (NEGF) formalism and calculated its characteristics by creating vacancies at different positions in the CNTFET channel. It has been observed that due to the creation of vacancy defects in the channel region of the CNTFET, the ON-current increases and OFF-current decreases in comparison to non-defective channel CNTFET. The results show that single, double, and triple vacancies have a very minor effect on the CNTFET conductivity. However, a huge reduction in CNTFET conductivity was observed when the density of vacancy defects in the channel was increased.

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter.

Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. However, no nanoelectronic architecture has been proposed which is solely based on carbon nanotubes and carbon nanotube field effect transistors. The reasons include lack of a self-assembly technology which could form complex carbon nanotube structures, or, absence of a reconfigurable carbon nanotube device which could provide functionality, reliability, and performance via reconfigurability. In this paper, I propose a novel double gate carbon nanotube field effect transistor (RDG-CNFET), which is reconfigurable to be open, short, FET, or via. Layers of orthogonal carbon nanotubes with electrically bistable molecules sandwiched at each crossing form a dense array of RDG-CNFETs and programmable interconnects, and constitute a nanoelectronic architecture of manufacturability (via regularity), reliability (via reconfigurability), and performance (via device density). Simulation based on CNFET and molecular device compact models demonstrates superior logic density, reliability, performance and power consumption of the proposed RDGCNFET based nanoelectronic circuits compared with the existing, e.g., molecular diode/MOSFET based nanoelectronic circuits.

A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .

This paper presents detailed analysis of bottom and top gate Polymeric/ Organic Thin Film Transistors (PTFTs/OTFTs) structures through two dimensional numerical device simulations. Further discussion shows various characteristics and properties of bottom gate bottom contact (BGBC), bottom gate top contact (BGTC), top gate top contact (TGTC) and top gate bottom contact (TGBC) Polymeric Transistors (PTs). Transistor based on organic semiconductor conducting polymers or small molecules used as active layer is identified to manage electric current flow which is known as PTFTs/OTFTs. The performance parameters of PTFTs are evaluated from output and transfer characteristics of different structures. Device characteristics parameters have been evaluated in terms of on/off current ratio, threshold voltage, field effect mobility, sub threshold slope, capacitance, transconductance and drive current. PTFTs/OTFTs are considered as promising switching device for future development of low-cost and large-area electronics applications such as flexible displays, organic memory, digital circuits and Sensors.

This paper provides a global overview of the radiofrequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes.

Semiconducting carbon nanotube (CNT) films are considered promising channel materials for constructing complementary metal‐oxide semiconducting (CMOS) field‐effect transistors (FETs) for future high‐performance integrated circuits (ICs). However, the poor performance of short channel n‐type FETs built on solution‐derived CNT films hinders the development of truly symmetric CMOS FETs, especially as the gate length scales down to the submicrometer region. The performance of short channel n‐type FETs is improved here by using scandium contacts accompanied by a doping channel and high‐performance and symmetrical CMOS FETs with a deep submicrometer gate length are fabricated for the first time. The n‐type and p‐type CNT FETs with a 150 nm gate length exhibit a maximum on‐state current Ion of ≈270 µA µm−1 and a peak transconductance gm of over 100 µS µm−1, representing the best CNT CMOS FETs thus far. Digital circuit and system benchmarking with the Intel circuit model indicates that the deep‐submicrometer CNT CMOS FETs show great advantages over the previously reported CMOS ICs based on CNT FETs or other semiconducting film‐based FETs.

In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

Novel carbon nanotube field effect transistor with graded double halo channel

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${L}_{\rm top}$</tex></formula> , with channel width <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${W} = 8 \ \mu$</tex></formula> m and bottom gate length fixed at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${L}_{\rm bot} = 4 \ \mu$</tex></formula> m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${-}$</tex></formula> 3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${L}_{\rm top}$</tex></formula> increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length.

The performance of carbon nanotube field‐effect transistor (CNFET) has been long predicted to surpass the existing field‐effect transistor. The performance is mostly contributed by the characteristic of the nanotube itself along with the design parameter of the whole transistor. This paper proposes a simulation study of drain control coefficient effect on CNFET performance as a whole device. The study comes from the analysis on simulation study of current‐voltage (I‐V) characteristic of ballistic CNFET. The simulation study used the MOSFET‐like CNFET mathematical model to establish the device output characteristic. From the simulation result obtained, it is found that the gate control coefficient contributes to a significant effect on the performance of CNFET particularly the level of leakage current and threshold voltage. The result shown the drain control parameter could help to improve the device performance but there is trade between leakage power and device response. Both parameters should be tuned in such a way that the leakage power could be suppressed and the device response is improved. It is concluded that the drain control coefficient should be picked so that the best performance can be achieved.

The ambipolar transporting characteristic is one of the most important factors that prevent the performance of Carbon Nanotube Field Effect Transistors (CNFETs) from further being improved. In order to reduce the ambipolar conductance and increase the ON-OFF current ratio of the device,a stair-case doping strategy in drain lead,which is suitable for not only the Conventional MOS-like CNFETs (C-CNFETs) but also Tunneling CNFET (T-CNFETs),is proposed in this paper. The non-equilibrium Greens function based simulation results show that this strategy can reduce the ambipolar conductance and increase the ON-OFF current ratio of the device effectively. Further study shows that many differences exist with using this stair-case doping strategy applied in C-CNFETs and T-CNFETs. First,the potential band pinning in stair-case doped C-CNFETs would weaken the ON-state performance of the device,while no band pinning exists in stair-case doped T-CNFETs. Second,applying such a stair-case doping strategy to both source and drain leads can further increase the device performances in C-CNFETs but not T-CNFEts. Third,the transporte property of T-CNFETs is dependent more strongly on the width of lightly doped drain region than that of C-CNFETs. However,certain device area would be costly because of using this stair-case doping strategy. So,much attention should be paid to the choice of device structure,doping concentration and lightly doped drain region width,to obtain a best tradeoff among speed,power and device area,in application.

Effect of parametric variation on the performance of single wall carbon nanotube based field effect transistor