Threshold voltage in junctionless nanowire transistors

This article presented at the IEEE Region 10 Annual International Conference [© 2016 IEEE] and the definite version is available at : https://10.1109/TENCON.2016.7848543. The article website is at: http://ieeexplore.ieee.org/document/7848543/

This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.

In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.

A simple analytical model for the drain current and threshold voltage for junctionless transistors with double gates is presented. This model provides a relatively exact and continuous description of junctionless transistor behaviour in all operating regions. Besides, the influence of different structure parameters such as the channel length, silicon layer thickness, gate oxide thickness, and the doping density on the drain current and threshold voltage is discussed. The analytical model solutions are compared with the numerical results obtained by using the COMSOL Multiphysics simulator. In addition, the influences of the channel length on the sub-threshold swing, threshold voltage, and Drain Induced Barrier Lowing are investigated in the simulation model. Moreover, by adding interface traps to the gate in the model, the effects of interface traps on transferring characteristics and the threshold voltage of junctionless transistor are studied.

The evolution of the field effect transistor technology has led to the reduction of the device dimensions to a few tenths of nanometers or even smaller. As the devices' dimensions are reduced, the occurrence of short-channel effects becomes unavoidable and degrades, to some extent, the electrical characteristics of the devices even when multiple gate or nanowire technologies are applied. This effect contributes to the variability of the devices, and, as a consequence, to its reliability.In ultimate devices such as nanowire FETs, reliability is inherently important since small variations in the electrical parameters, e.g. the drain current or the threshold voltage, can significantly affect the device performance in a circuit application. Several reliability issues such as Self-Heating Effect (SHE), Negative-Bias Temperature Instabilities (NBTI), Low-Frequency Noise (LFN), Random Telegraph Noise (RTN), and Time-Dependent Dielectric Breakdown (TDDB) are geometry-dependent and become more important for short-channel devices. Most of these parameters are strongly affected by the occurrence of defects or traps in the interface between the active region and gate dielectric. Thus, the analysis of the quality of the semiconductor-dielectric interface has become increasingly important and can be performed through different techniques. Each of them demands different facilities and can deliver different information from DUTs.Low-Frequency Noise Several is one of the most complete analyses that can be performed in terms of reliability in ultimate devices, as it enables access to several parameters with respect to traps’ characteristics. By the fundamental shape of the drain current noise spectral density (SId) as a function of the frequency (f), it is possible to verify the presence of trap centers, which overwhelm the overall noise, such that SId presents a plateau followed by a 1/f2 decay with frequency increase, the so-called G-R noise, instead of the standard 1/f shape, as shown in Fig. 1 for junctionless transistors. Also, through some mathematical manipulation in the case of 1/f shape, one can extract the active trap density (Nit), its dependence on bias conditions (Fig. 2(A)), and the trap depth inside the dielectric layer (Fig. 2(B)). If structures with different geometrical characteristics, such as different dielectric thicknesses need to be compared, it is useful to calculate the Gate Noise Parameter (GNP), which enables a fair comparison between different samples. This parameter can also be used to indicate the nature of the energy distribution of traps. For samples with 1/f2 aspect, where G-R noise is dominant, the activation energy of the dominant trap center can also be extracted through the measurement of LFN as a function of the temperature by plotting the Arrhenius curve. However, the low-frequency noise characterization requires a specific setup, including an LFN analyzer, Low-Noise Amplifiers (LNAs), and, frequently, strategies to compensate for the instrumentation background noise. Besides that, there are some situations in which the determination of Nit through LFN is difficult, as in the case of NBTI occurrence, where traps are generated along time.Therefore, other techniques can be applied either to extract parameters not easily obtained through LFN or to avoid the use of a specific setup. In this case, it could also be possible to extract trap density through capacitance curves, where a C-V meter is needed, or even through current curves (ID) as a function of time (t) or gate bias (VG). The ID-t and ID-VG characteristics can be an alternative to estimate active trap density and its profile along the bandgap, for example. Through a charge-pumping-like method, a pulsed signal can be applied in the gate of a transistor. Thus, the drain current will follow the gate bias, and the rise and fall times of ID can be associated with the occupation and release of traps, allowing for an estimation of Nit. It is worth mentioning that the accuracy of this estimation is better for devices with larger total trap density (N0) as stated in Fig. 3. Finally, there are methods that permit the extraction of active trap density and its profile along bandgap directly through ID-VG curves. In long devices, the active trap density can be estimated through the behavior of subthreshold swing, which is directly correlated to Nit and, in some ultimate devices, such as junctionless nanowire transistors, the variation of the substrate bias permits extraction of Nit profile along the bandgap (Fig. 4). This is only possible because, in these devices, the surface potential is not pinned at twice the Fermi potential in the conduction regime as it occurs in inversion mode transistors. Figure 1

In the devices with nanowire channel, series resistance is an important parameter. As the channel length is scaled down, channel resistance is gradually small and it has therefore become an important issue to keep the value of series resistance smaller than channel resistance in order to ensure the device performance. Moreover, the series resistance fluctuates in the devices; it is mainly due to its three dimensional contact configuration between the source/drain and channel. Due to these reasons, therefore, it is important to extract the series resistance and to examine its behavior in terms of appropriate device parameters and the complexity of contact configuration. Recently, the junctionless nanowire transistor (JNT) is spotlighted due to its high on/off ratio, excellent gate controllability through multiple-gate structure, the immunity of short channel effect such as DIBL and threshold voltage roll-off, and the extremely simple fabrication process. Although many studies have been carried out for the JNT, the research on the comparative analysis of the series resistance of between the JNT and the inversion mode nanowire FET was not performed yet. In this paper, we demonstrated and compared the extracted series resistance between fabricated JNTs and inversion mode nanowire FET (IMN-FET) through the method based on Y-function. This technique provides to extract the series resistance of both devices obviously and accurately. The observed data are discussed based on the existing theories.

Optical diagnostics of plasma chemistries and chamber conditions in gate oxide stack etch

In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/ process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures.

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.

The characteristics of junctionless(JL) SON(Silicon on Nothing) FinFET, JL Bulk FinFET and SOI(Silicon on Insulator) JNT(Junctionless nanowire transistor) transistors were compared. A Silicon on nothing transistor have substrate with air filled dielectric. JL SON FinFET have better on/off current ratio and short channel effect (SCE) by reducing channel thickness due to substrate channel junction. The subthreshold slope is 63.2m V/dec and DIBL 82.68mV. the on/off current ratio is approximately 105 at channel thickness of 10nm. The variation in threshold voltage as Nsub varies from 1017 to 1018 cm−3 is about 33%. JL SON FinFET gives better on/off current ratio with the variation of work function.

Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor

The gate‐all‐around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub‐5 nm technology nodes. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here a dual‐gated junctionless nanowire p‐type field effect transistor is demonstrated using tellurium nanowire as the channel. The dangling‐bond‐free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling‐bond‐free, high quality hBN gate dielectric, allows for a phonon‐limited field effect hole mobility of 570 cm2 V−1 s−1 at 270 K, which is well above state‐of‐the‐art strained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm2 V−1 s−1 and becomes primarily limited by Coulomb scattering. The combination of an electron affinity of ≈4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal‐contact interface, which is remarkable for reduction of contact resistance in a highly scaled transistor. Exploiting these properties, coupled with the dual‐gated operation, we achieve a high drive current of 216 μA μm−1 while maintaining an on‐off ratio in excess of 2 × 104. The findings have intriguing prospects for alternate channel material based next‐generation electronics.

The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77–410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (Vth), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both Vth and Ion showed significant doping concentration dependences for JL devices with doping concentrations of 1 × 1019 and 5 × 1019 cm−3. However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 1020 cm−3.

Modeling of bias-induced changes of organic field-effect transistor characteristics