Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

The evolution of the field effect transistor technology has led to the reduction of the device dimensions to a few tenths of nanometers or even smaller. As the devices' dimensions are reduced, the occurrence of short-channel effects becomes unavoidable and degrades, to some extent, the electrical characteristics of the devices even when multiple gate or nanowire technologies are applied. This effect contributes to the variability of the devices, and, as a consequence, to its reliability.In ultimate devices such as nanowire FETs, reliability is inherently important since small variations in the electrical parameters, e.g. the drain current or the threshold voltage, can significantly affect the device performance in a circuit application. Several reliability issues such as Self-Heating Effect (SHE), Negative-Bias Temperature Instabilities (NBTI), Low-Frequency Noise (LFN), Random Telegraph Noise (RTN), and Time-Dependent Dielectric Breakdown (TDDB) are geometry-dependent and become more important for short-channel devices. Most of these parameters are strongly affected by the occurrence of defects or traps in the interface between the active region and gate dielectric. Thus, the analysis of the quality of the semiconductor-dielectric interface has become increasingly important and can be performed through different techniques. Each of them demands different facilities and can deliver different information from DUTs.Low-Frequency Noise Several is one of the most complete analyses that can be performed in terms of reliability in ultimate devices, as it enables access to several parameters with respect to traps’ characteristics. By the fundamental shape of the drain current noise spectral density (SId) as a function of the frequency (f), it is possible to verify the presence of trap centers, which overwhelm the overall noise, such that SId presents a plateau followed by a 1/f2 decay with frequency increase, the so-called G-R noise, instead of the standard 1/f shape, as shown in Fig. 1 for junctionless transistors. Also, through some mathematical manipulation in the case of 1/f shape, one can extract the active trap density (Nit), its dependence on bias conditions (Fig. 2(A)), and the trap depth inside the dielectric layer (Fig. 2(B)). If structures with different geometrical characteristics, such as different dielectric thicknesses need to be compared, it is useful to calculate the Gate Noise Parameter (GNP), which enables a fair comparison between different samples. This parameter can also be used to indicate the nature of the energy distribution of traps. For samples with 1/f2 aspect, where G-R noise is dominant, the activation energy of the dominant trap center can also be extracted through the measurement of LFN as a function of the temperature by plotting the Arrhenius curve. However, the low-frequency noise characterization requires a specific setup, including an LFN analyzer, Low-Noise Amplifiers (LNAs), and, frequently, strategies to compensate for the instrumentation background noise. Besides that, there are some situations in which the determination of Nit through LFN is difficult, as in the case of NBTI occurrence, where traps are generated along time.Therefore, other techniques can be applied either to extract parameters not easily obtained through LFN or to avoid the use of a specific setup. In this case, it could also be possible to extract trap density through capacitance curves, where a C-V meter is needed, or even through current curves (ID) as a function of time (t) or gate bias (VG). The ID-t and ID-VG characteristics can be an alternative to estimate active trap density and its profile along the bandgap, for example. Through a charge-pumping-like method, a pulsed signal can be applied in the gate of a transistor. Thus, the drain current will follow the gate bias, and the rise and fall times of ID can be associated with the occupation and release of traps, allowing for an estimation of Nit. It is worth mentioning that the accuracy of this estimation is better for devices with larger total trap density (N0) as stated in Fig. 3. Finally, there are methods that permit the extraction of active trap density and its profile along bandgap directly through ID-VG curves. In long devices, the active trap density can be estimated through the behavior of subthreshold swing, which is directly correlated to Nit and, in some ultimate devices, such as junctionless nanowire transistors, the variation of the substrate bias permits extraction of Nit profile along the bandgap (Fig. 4). This is only possible because, in these devices, the surface potential is not pinned at twice the Fermi potential in the conduction regime as it occurs in inversion mode transistors. Figure 1

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage.

This letter investigates the bias-dependent low frequency noise of single layer graphene field-effect transistors. Noise measurements have been conducted with electrolyte-gated graphene transistors covering a wide range of gate and drain bias conditions for different channel lengths. A new analytical model that accounts for the propagation of the local noise sources in the channel to the terminal currents and voltages is proposed in this paper to investigate the noise bias dependence. Carrier number and mobility fluctuations are considered as the main causes of low frequency noise and the way these mechanisms contribute to the bias dependence of the noise is analyzed in this work. Typically, normalized low frequency noise in graphene devices has been usually shown to follow an M-shape dependence versus gate voltage with the minimum near the charge neutrality point (CNP). Our work reveals for the first time the strong correlation between this gate dependence and the residual charge which is relevant in the vicinity of this specific bias point. We discuss how charge inhomogeneity in the graphene channel at higher drain voltages can contribute to low frequency noise; thus, channel regions nearby the source and drain terminals are found to dominate the total noise for gate biases close to the CNP. The excellent agreement between the experimental data and the predictions of the analytical model at all bias conditions confirms that the two fundamental 1/f noise mechanisms, carrier number and mobility fluctuations, must be considered simultaneously to properly understand the low frequency noise in graphene FETs. The proposed analytical compact model can be easily implemented and integrated in circuit simulators, which can be of high importance for graphene based circuits' design.

The advance of technology demands an extreme miniaturization of electronic devices, reaching prohibitive levels from the point of view of the short channel effects (SCEs) as well as manufacturers' limitations. One important cumbersome task in ultimate devices consists of the formation of the source and drain regions that demand the variation of doping types and concentrations in several orders of magnitude in very short dimensions. Some techniques are proposed to overcome these unwanted effects, such as the introduction of multi-gate structures as well as the use of SOI technology that isolates the active silicon layer from the substrate. Even though, in ultimate technological nodes this is still a major issue.Aiming to minimize these unwanted effects, Junctionless Nanowire Transistors (JNTs) were proposed. They consist of a high-doped nanowire with the same doping type in the source/channel/drain regions, commonly surrounded by an oxide/metal stack on an SOI wafer. These devices usually have multiple gates, improving their gate electrostatic control over the channel charges and improving the immunity to SCEs. As no junctions of the source and the drain to the channel are formed, this device is manufactured in a way that the difference between the channel and gate work functions makes the device fully depleted, blocking the current flow.JNTs can be fabricated with dielectric spacers, that form an extension between channel and source/drain regions. This permits the depletion region due to the gate to be extended towards the source and drain regions in the off-state and in partial depletion regime, making the effective channel length LEFF longer than the mask channel length and reducing the SCEs.The estimation of LEFF is not a simple task, and some experimental methods have been proposed in the literature to extract it. One of the methods, based on the total gate capacitance extraction, can only be applied to large devices due to the limitations of measuring the extremely low capacitances observed in short and narrow devices, while another one, based on the subthreshold slope (SS) has only been validated for low drain bias (VDS). However, studies are still needed to evaluate and improve these methods. So, the objective of this work is to study and extract the LEFF of JNTs through SS, for high VDS bias when the SCEs are present.This work considers experimental devices provided by CEA-LETI, with channel lengths of 30 and 100 nm, source and drain lengths of 15 nm, effective gate oxide thickness of 1.5 nm, buried oxide of 150 nm, width of 20 nm, height of 10 nm and doping concentrations of 5 x 1018 and 1 x 1019 cm-3 operating at 300K.To extract the SS of the devices, the drain current (ID) curves were obtained as a function of the gate voltage (VGS), as shown in Fig. 1(A) and (B) for P- and N-type MOSFETs, respectively. In the sequence, SS was extracted through the plateau obtained by the inverse of the derivative of the logarithm of ID with respect to gate voltage as presented in Fig. 2. LEFF has been extracted for experimental devices through the relationship between a long and a short device SS, as indicated in Eq. (1). This equation assumes that the minimum potential is located at the center of the channel of the device, which is valid for low drain bias. However, for high VDS bias (for 500 mV or higher) the minimum potential moves towards the source side of the transistor. So, aiming to allow its application in devices biased with high VDS, the SS needs to be divided by a factor that represents the rate of the minimum potential shift towards the source with VDS increase. In the present work, this factor was experimentally determined as 1.08.The LEFF of the devices is exhibited in Table 1, which presents the comparison between the LEFF obtained by Eq. (1) and Eq. (2), which consists of an analytical expression for the estimation of LEFF based on the physical characteristic of the devices considering different biasing conditions. However, as there could be imprecision between the target and actual characteristics of the devices, Eq. (1) was proposed to enable LEFF estimation directly from experimental measurements. The LEFF was extracted for different doping concentrations and doping types and resulted in LEFF higher than the mask channel length in all cases. The method is able to capture the dependence on doping concentration and showed adequate results when applied for VDS values, showing a maximum error of 16% with respect to the analytical model of Eq. (2). Figure 1

In the devices with nanowire channel, series resistance is an important parameter. As the channel length is scaled down, channel resistance is gradually small and it has therefore become an important issue to keep the value of series resistance smaller than channel resistance in order to ensure the device performance. Moreover, the series resistance fluctuates in the devices; it is mainly due to its three dimensional contact configuration between the source/drain and channel. Due to these reasons, therefore, it is important to extract the series resistance and to examine its behavior in terms of appropriate device parameters and the complexity of contact configuration. Recently, the junctionless nanowire transistor (JNT) is spotlighted due to its high on/off ratio, excellent gate controllability through multiple-gate structure, the immunity of short channel effect such as DIBL and threshold voltage roll-off, and the extremely simple fabrication process. Although many studies have been carried out for the JNT, the research on the comparative analysis of the series resistance of between the JNT and the inversion mode nanowire FET was not performed yet. In this paper, we demonstrated and compared the extracted series resistance between fabricated JNTs and inversion mode nanowire FET (IMN-FET) through the method based on Y-function. This technique provides to extract the series resistance of both devices obviously and accurately. The observed data are discussed based on the existing theories.

In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.

Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.

This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design- Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.

This paper presents a compact analytical model for the static and dynamic electrical characteristics of Junctionless Nanowire Transistors. The static drain current model formulation is derived from the 2D solution of the Poisson equation with appropriate boundary conditions and long-channel devices, leading to a continuous effective surface potential that accounts for the conduction in partial depletion and accumulation regimes. The long-channel model is modified to account for short-channel effects by using the coupled solution of 3D Laplace equation with the 2D Poisson equation. The substrate bias influence on the drain current is also included in the model formulation. The charges at the device terminals are differentiated with respect to the applied biases leading to an analytical description of the transconductances and transcapacitances. The proposed model is validated using experimental data at different bias conditions and temperatures, showing very good agreement.

With the development of down-scaling of CMOS technology for low power, mixed-signal, and high frequency applications, the optimal high frequency performance is shown to be shifted from lower moderate inversion toward weak inversion regimes. High-frequency noise model is a prerequisite for designing the radio frequency and millimeter-wave circuits, and is essential for the noise analysis of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, based on the physical structure of 40 nm MOSFET and by considering the drift-diffusion equation and charge conservation law, accurate physics-based unified high-frequency noise model is developed for induced gatecurrent noise and its cross-correlation with drain-current noise under different bias conditions, which is used to describe the frequency and bias dependence of 40 nm MOSFET from weak inversion to strong inversion regime. Especially, the effective gate overdrive is explicitly included in unified noise model to offer excellent accuracy, continuity and smoothness, and this makes the proposed analytical models convenient to directly reflect the relationship between the noise model and bias condition. Besides, new analytical model is derived for the induced-gate current noise and its cross-correlation term of weakly inverted MOSFET. These simple expressions not only serve as the asymptotic limit for the validation of the proposed physics-based unified model, but also provide a clearer insight into and better understanding of the gate noise behavior and their cross-correlation in the weak-inversion region. Moreover, in terms of the proposed subthreshold noise model, the charge of weak inversion rather than the normal effective channel thickness approximation is involved. In this way, the model accuracy can be improved. Furthermore, a detailed derivation and discussion are presented by analyzing the physics-based noise generation mechanism of transistor including the channel thermal noise and the shot noise based on the small-signal equivalent circuit of the 40 nm MOSFET device. Using these expressions it is possible to extract the values of all the noise model parameters directly from measurement. The proposed model is demonstrated by using noise data from both measurement and the noise simulation. Excellent agreement between simulated and measured noise data shows that the proposed model can be used for predicting the noise behavior of 40 nm MOSFET under different dimensions and operating conditions. The applicability of reported model for drain-current noise is also verified. As far as small-signal (i.e., linear) bias-dependent operation is concerned, it is shown how most of the findings of this work can also be used to predict the data of long channel devices in the strong-inversion regimes.

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

We present in this work the first characterization and modeling of low-frequency noise for SiGe-NPNs and SiGe-PNPs operating in the inverse mode from an advanced SiGe RF technology on SOI. Comparison is made between low-frequency noise in the forward and inverse modes. Impact of selective implanted collector (SIC) on inverse mode low-frequency noise is investigated. Finally, a methodology for low-frequency noise compact modeling in the inverse mode of operation is discussed.

The gate‐all‐around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub‐5 nm technology nodes. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here a dual‐gated junctionless nanowire p‐type field effect transistor is demonstrated using tellurium nanowire as the channel. The dangling‐bond‐free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling‐bond‐free, high quality hBN gate dielectric, allows for a phonon‐limited field effect hole mobility of 570 cm2 V−1 s−1 at 270 K, which is well above state‐of‐the‐art strained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm2 V−1 s−1 and becomes primarily limited by Coulomb scattering. The combination of an electron affinity of ≈4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal‐contact interface, which is remarkable for reduction of contact resistance in a highly scaled transistor. Exploiting these properties, coupled with the dual‐gated operation, we achieve a high drive current of 216 μA μm−1 while maintaining an on‐off ratio in excess of 2 × 104. The findings have intriguing prospects for alternate channel material based next‐generation electronics.

Advances in technology has allowed us to demand for high speed and low power devices in modern chips. These transistors are scaled down and examined with multi-gate architecture in order to improve electrostatic control over the channel and reduce power consumption. A novel dual-gate gate-all-around (GAA) junctionless nanowire transistor (JNT) is addressed in this work. Using TCAD device modeling, we report a process variability analysis and explored the device characteristics. A cylindrical nanowire with a channel length of 10 nm and a diameter of 5 nm is employed to study the process sensitivity of the device. A 1 nm thick HfO2 gate is used as a dielectric material. Analysis from deep depletion to strong accumulation mode with a 2e19 cm−3 n-type channel doping (Vds = 0.8V and T = 300 K) is reported. The dual-gate GAA JNT shows an improved electrical behavior with a variation to channel doping, channel diameter, channel length and oxide thickness. It also has an enhanced short channel behavior such as high Ion/Ioff (>106), good sub threshold slope (∼68 mV/decade) and low drain induced barrier lowering (∼8mV/V) compared to conventional inversion mode transistors and regular nanowire GAA devices that makes the device a candidate for energy efficiency improvements.

This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (IM) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage.