Static and dynamic compact analytical model for junctionless nanowire transistors

The goal of this research is to develop a Dynamic Compact Thermal Model (DCTM) of electronic packages. The general objectives of thermal modeling are to increase the accuracy of electrical analysis by taking the effect of temperature variation into consideration, predicting the reliability of the product, and acquiring the information which is necessary to design the cooling system in order to enhance the performance of the electronic systems. The project is focused on generating the dynamic compact thermal model of electronic packages so that the transient thermal behaviors of the package could be predicted fast and accurately. The approach proposed by DELPHI consortium (a collaborative European project) for static compact thermal model generation is extended in this work to generate the dynamic compact model of a BGA package represented by a RC network or admittance matrix. Two steps performed as the methodology of dynamic compact model generation in this work are: 1- A static compact thermal model of BGA package is generated and validated from the static thermal simulation and 2- A RC network is proposed as the contribution of this work and calculated by optimization as the dynamic compact thermal model of the package using the data of transient simualtion. The size of the proposed RC network then is optimized by eliminating some capacitors from the original RC network and validated by comparing its output to the ouptut of finite element simulation. COMSOL©, a Finite element analysis tool is used for thermal simulation and detailed steady state and transient model generation. The optimization algorithm implemented for both static and dynamic compact model generation is Nelder-Mead multidimensional optimization which is realized by MATLAB© programming. The obtained results from the compact models for both static and dynamic analysis of the BGA package are in agreement with the detailed thermal model results and with the available results in literature.

We present a 2D physics based compact model of the double gate (DG) and the gate‐all‐around (GAA) MOSFET, with emphasis on short‐channel devices of nano‐scale dimensions. The compact model is based on a preprocessing routine based on a self‐consistent framework for electrostatics modeling. For sub‐threshold conditions, we assume that the device body is dominated by the solution of the 2D Laplace electrostatics. This assumption is based on the fact that the field strength at the gates emerging from the mobile charge carriers and the doping are much weaker than the fields related to the capacitive coupling between the contacts and the gates. Therefore, we neglect the body charge term in Poisson's equation, converting it to a Laplace equation. Near threshold, the influence of the electronic charge on the electrostatics is taken into account in the framework model in a precise, self‐consistent manner by combining suitable model expressions with the 2D Poisson's equation in the device body. To this end, we consider the self‐consistent potential distributions along the two symmetry axis. Suitable modeling expressions are applied, whose parameters are determined from the boundary conditions and by enforcing self‐consistency using Poisson's equation. The framework and the compact model give excellent results when compared with numerical simulations. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

A new compact modeling approach is presented which describes the full current-voltage (I-V) characteristic of high-performance (aggressively scaled-down) tunneling field-effect-transistors (TFETs) based on homojunction direct-bandgap semiconductors. The model is based on an analytic description of two key features, which capture the main physical phenomena related to TFETs: (1) the potential profile from source to channel and (2) the elliptic curvature of the complex bands in the bandgap region. It is proposed to use 1D Poisson's equations in the source and the channel to describe the potential profile in homojunction TFETs. This allows to quantify the impact of source/drain doping on device performance, an aspect usually ignored in TFET modeling but highly relevant in ultra-scaled devices. The compact model is validated by comparison with state-of-the-art quantum transport simulations using a 3D full band atomistic approach based on non-equilibrium Green's functions. It is shown that the model reproduces with good accuracy the data obtained from the simulations in all regions of operation: the on/off states and the n/p branches of conduction. This approach allows calculation of energy-dependent band-to-band tunneling currents in TFETs, a feature that allows gaining deep insights into the underlying device physics. The simplicity and accuracy of the approach provide a powerful tool to explore in a quantitatively manner how a wide variety of parameters (material-, size-, and/or geometry-dependent) impact the TFET performance under any bias conditions. The proposed model presents thus a practical complement to computationally expensive simulations such as the 3D NEGF approach.

Numerical simulation and modeling of short-channel three-dimensional nano MISFET for the application in ULSI circuits

The homotopy decomposition method, a relatively new analytical method, is used to solve the 2D and 3D Poisson equations and biharmonic equations. The method is chosen because it does not require the linearization or assumptions of weak nonlinearity, the solutions are generated in the form of general solution, and it is more realistic compared to the method of simplifying the physical problems. The method does not require any corrected function or any Lagrange multiplier and it avoids repeated terms in the series solutions compared to the existing decomposition method including the variational iteration method, the Adomian decomposition method, and Homotopy perturbation method. The approximated solutions obtained converge to the exact solution as tends to infinity.

This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.

PurposeThe purpose of this paper is to develop a dynamic compact thermal model (DCTM) of electronic packages. This model is a necessary tool for rapid thermal analysis of the systems which we exposed to boundary condition variation and/or power switching mode such as mobile systems and battery powered systems.Design/methodology/approachThe methodology of compact model generation used was based on generating the transient dynamic detailed finite element thermal model of a package, designing a resistor/capacitor network topology representative of the dynamic detailed model, calculating the resistors'/capacitors' value by optimization method and validation efforts. The method is demonstrated for a ball grid array (BGA) package, a commonly used modern electronic package.FindingsBased on the obtained results, it can be concluded that the dynamic thermal behavior of a BGA package can be accurately described by a generated dynamic compact model in terms of predicted junction temperature response and heat flux of the desired locations of the package.Originality/valueThis model is capable of calculating the temperatures and heat fluxes at desired locations which can help the designer to perform the thermal analysis much faster and easier with the required accuracy.

Compact Modeling of Physical Mechanisms Present in the Weak Breakdown Regime of Advanced Si and SiGe Bipolar Transistors

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage.

The advance of technology demands an extreme miniaturization of electronic devices, reaching prohibitive levels from the point of view of the short channel effects (SCEs) as well as manufacturers' limitations. One important cumbersome task in ultimate devices consists of the formation of the source and drain regions that demand the variation of doping types and concentrations in several orders of magnitude in very short dimensions. Some techniques are proposed to overcome these unwanted effects, such as the introduction of multi-gate structures as well as the use of SOI technology that isolates the active silicon layer from the substrate. Even though, in ultimate technological nodes this is still a major issue.Aiming to minimize these unwanted effects, Junctionless Nanowire Transistors (JNTs) were proposed. They consist of a high-doped nanowire with the same doping type in the source/channel/drain regions, commonly surrounded by an oxide/metal stack on an SOI wafer. These devices usually have multiple gates, improving their gate electrostatic control over the channel charges and improving the immunity to SCEs. As no junctions of the source and the drain to the channel are formed, this device is manufactured in a way that the difference between the channel and gate work functions makes the device fully depleted, blocking the current flow.JNTs can be fabricated with dielectric spacers, that form an extension between channel and source/drain regions. This permits the depletion region due to the gate to be extended towards the source and drain regions in the off-state and in partial depletion regime, making the effective channel length LEFF longer than the mask channel length and reducing the SCEs.The estimation of LEFF is not a simple task, and some experimental methods have been proposed in the literature to extract it. One of the methods, based on the total gate capacitance extraction, can only be applied to large devices due to the limitations of measuring the extremely low capacitances observed in short and narrow devices, while another one, based on the subthreshold slope (SS) has only been validated for low drain bias (VDS). However, studies are still needed to evaluate and improve these methods. So, the objective of this work is to study and extract the LEFF of JNTs through SS, for high VDS bias when the SCEs are present.This work considers experimental devices provided by CEA-LETI, with channel lengths of 30 and 100 nm, source and drain lengths of 15 nm, effective gate oxide thickness of 1.5 nm, buried oxide of 150 nm, width of 20 nm, height of 10 nm and doping concentrations of 5 x 1018 and 1 x 1019 cm-3 operating at 300K.To extract the SS of the devices, the drain current (ID) curves were obtained as a function of the gate voltage (VGS), as shown in Fig. 1(A) and (B) for P- and N-type MOSFETs, respectively. In the sequence, SS was extracted through the plateau obtained by the inverse of the derivative of the logarithm of ID with respect to gate voltage as presented in Fig. 2. LEFF has been extracted for experimental devices through the relationship between a long and a short device SS, as indicated in Eq. (1). This equation assumes that the minimum potential is located at the center of the channel of the device, which is valid for low drain bias. However, for high VDS bias (for 500 mV or higher) the minimum potential moves towards the source side of the transistor. So, aiming to allow its application in devices biased with high VDS, the SS needs to be divided by a factor that represents the rate of the minimum potential shift towards the source with VDS increase. In the present work, this factor was experimentally determined as 1.08.The LEFF of the devices is exhibited in Table 1, which presents the comparison between the LEFF obtained by Eq. (1) and Eq. (2), which consists of an analytical expression for the estimation of LEFF based on the physical characteristic of the devices considering different biasing conditions. However, as there could be imprecision between the target and actual characteristics of the devices, Eq. (1) was proposed to enable LEFF estimation directly from experimental measurements. The LEFF was extracted for different doping concentrations and doping types and resulted in LEFF higher than the mask channel length in all cases. The method is able to capture the dependence on doping concentration and showed adequate results when applied for VDS values, showing a maximum error of 16% with respect to the analytical model of Eq. (2). Figure 1

The numerical simulation of electromagnetic problems is usually complex and time‐consuming, so a fast and accurate solver is urgently needed. In this paper, a deep learning method based on conditional generative adversarial network (CGAN) is used to solve the 2D Poisson's equation in electrostatic field. The relative permittivity distribution and source charge distribution in the two dimensional region are regarded as label of CGAN, and the potential distribution is the real image or generated image corresponding to the label. This deep learning network can be trained by reasonably designing the loss functions of generator and discriminator, and based on a large amount of samples obtained by the finite difference method. The average relative prediction error of the trained CGAN for all samples is less than 0.5%, with a significant reduction in prediction time, while that of convolution neural network (CNN) is less than 1.5%. Furthermore, the average relative prediction error of CGAN is less than 1% for the scenes different from those of training and testing samples, including triangle, square, and pentagon. The prediction results indicate that CGAN has stronger learning ability and fast prediction speed, and can be used as a fast solver for electromagnetic numerical problems.

In this work, we have correlated the degradation by Negative Bias Temperature Instability (NBTI) in MOS Junctionless Nanowire Transistors (JNTs) to the electric field inside the devices. We have measured samples with doping concentrations of 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , biased at two different drain voltages, with several channel lengths (L) and widths (W). To extend the analysis, aiming at the understanding the physical behavior of the devices, we performed simulations of NBTI considering devices with similar characteristics. As a result, a higher degradation by the NBTI effect was obtained for the JNTs with lower doping concentration and shorter channel. The behavior of the NBTI has been correlated to the electric field of the devices and it is shown that the electric field becomes important mainly in accumulation regime.

This paper presents a new conformal mapping method to solve 2D Laplace and Poisson equations in MOS devices. More specifically, it consists of an analytical solution of the 2D Laplace equation in a rectangular domain with Dirichlet boundary conditions, with arbitrary values on the boundaries. The advantages of the new method are that all four edges of the rectangle are taken into account and the solution consists of closed-form analytical expressions, which make it fast and suitable for compact modeling. The new model was validated against other similar methods. It was found that the new model is much faster, easier to implement, and avoids many numerical issues, especially near the boundaries, at the cost of a very small loss in accuracy.

0C (43K) in the polar shadows), makes operation of the electronics sub-systems on the surface of the Moon exceptionally difficult, but is nonetheless required for the envisioned complex suite of electronics systems used in sensing, actuation, and control of robotic systems. Such applications are typically fairly low frequency in nature (e.g., < 100 MHz), hence not requiring the most aggressively scaled CMOS technology; however, a full suite of mixed-signal circuit building blocks, and reliable operation of those circuits across extremely large variations in temperature (e.g., +120 to -230C) is needed. Adequate device reliability must clearly be achieved to accomplish this task. CMOS device degradation due to hot carriers effect (HCE) is known to be considerably worse at low temperatures [2]. Device lifetime data at cryogenic temperatures, and a solid understanding of the corresponding degradation mechanisms, are thus critical in this context of space electronics, and are addressed in this work. The Si CMOS devices investigated here are from an advanced 0.5µm SiGe BiCMOS technology, with a fixed channel width of 10.0 µm, and effective gate lengths ranging from 0.35 µm (minimum geometry), to 5.0 µm. The devices were characterized on a custom cryogenic probe system from 300K down to 43 K (-230 0 C). For brevity we will focus on the nFET data, since it represents the worst case in this technology. Fig. 1 and 2 shows typical I-V characteristics for the CMOS devices at different temperatures. The current drive capability increases significantly for the same bias conditions, as the temperature decreases. The nFET lifetime was inferred using stress-induced changes to the ID-VG characteristics. The lifetime τ is defined here as the inferred stress time for which a certain parameter of the ID-VG characteristics has shifted by a predefined amount (e.g., 10% degradation of gm). A typical lifetime assessment analysis using the ID-VG characteristics for a 1.0 µm nFET are shown in Fig. 3 and Fig. 4. The slope of 0.6 for the linear fitting in Fig. 4 suggests that interface state generation is responsible for the observed device degradation at the maximum substrate current (VG ≈ ½ VD); while that of 0.3 for the maximum gate current bias condition (VG = VD) suggests that oxide trapped charge dominates [3]. For the nFETs operating at 300K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias. There has been speculation that the worst case bias conditions for hot carrier degradation can, however, be a function of temperature [4]. It can be verified from Fig. 4 that for this technology, maximum substrate current is indeed the worst bias condition, at least down to 82K, and hence was the condition used here for device lifetime evaluation. The substrate current is comprised of the generated hot carriers, and is thus a good monitoring parameter for HCE in practical measurements. Fig. 5 and Fig. 6 show the effects of temperature and gate length on substrate current, respectively. It can be seen from Fig. 5 that the maximum substrate current under the same bias condition increases by 3x as temperature decreases from 300K to 43K; while Fig. 6 suggests that the maximum substrate current increases by more than 10x as L shrinks from 1.0 µm to 0.35 µm, and becomes negligible as L increases to 5.0 µm. This suggests that HCE is impacted more by device geometry than by the temperature. Fig. 7 shows the inferred lifetime at different drain bias’ at different temperatures. As seen in Fig. 7, τ decreases by ~10x as the temperature is reduced from 300K to 82K. Furthermore, τ differs by more than 100x between the 1.0 µm and 0.35/5 µm transistors, and hence the longer-channel devices are preferred for cryogenic applications of this technology Assuming fast interface trap generation dominates the HCE degradation, plotting τID versus ISUB/ID on a log-log scale should yield a straight line behavior [5]. The critical electron energy for generating an interface trap is calculated to be 3.9 eV from the slop of the line. Both the slope and the critical energy from Fig. 8 correlate well with literature data (2.9 and 3.7 eV in [5]), suggesting that interface state generation is the dominant limiting reliability factor at low temperatures.

The evolution of the field effect transistor technology has led to the reduction of the device dimensions to a few tenths of nanometers or even smaller. As the devices' dimensions are reduced, the occurrence of short-channel effects becomes unavoidable and degrades, to some extent, the electrical characteristics of the devices even when multiple gate or nanowire technologies are applied. This effect contributes to the variability of the devices, and, as a consequence, to its reliability.In ultimate devices such as nanowire FETs, reliability is inherently important since small variations in the electrical parameters, e.g. the drain current or the threshold voltage, can significantly affect the device performance in a circuit application. Several reliability issues such as Self-Heating Effect (SHE), Negative-Bias Temperature Instabilities (NBTI), Low-Frequency Noise (LFN), Random Telegraph Noise (RTN), and Time-Dependent Dielectric Breakdown (TDDB) are geometry-dependent and become more important for short-channel devices. Most of these parameters are strongly affected by the occurrence of defects or traps in the interface between the active region and gate dielectric. Thus, the analysis of the quality of the semiconductor-dielectric interface has become increasingly important and can be performed through different techniques. Each of them demands different facilities and can deliver different information from DUTs.Low-Frequency Noise Several is one of the most complete analyses that can be performed in terms of reliability in ultimate devices, as it enables access to several parameters with respect to traps’ characteristics. By the fundamental shape of the drain current noise spectral density (SId) as a function of the frequency (f), it is possible to verify the presence of trap centers, which overwhelm the overall noise, such that SId presents a plateau followed by a 1/f2 decay with frequency increase, the so-called G-R noise, instead of the standard 1/f shape, as shown in Fig. 1 for junctionless transistors. Also, through some mathematical manipulation in the case of 1/f shape, one can extract the active trap density (Nit), its dependence on bias conditions (Fig. 2(A)), and the trap depth inside the dielectric layer (Fig. 2(B)). If structures with different geometrical characteristics, such as different dielectric thicknesses need to be compared, it is useful to calculate the Gate Noise Parameter (GNP), which enables a fair comparison between different samples. This parameter can also be used to indicate the nature of the energy distribution of traps. For samples with 1/f2 aspect, where G-R noise is dominant, the activation energy of the dominant trap center can also be extracted through the measurement of LFN as a function of the temperature by plotting the Arrhenius curve. However, the low-frequency noise characterization requires a specific setup, including an LFN analyzer, Low-Noise Amplifiers (LNAs), and, frequently, strategies to compensate for the instrumentation background noise. Besides that, there are some situations in which the determination of Nit through LFN is difficult, as in the case of NBTI occurrence, where traps are generated along time.Therefore, other techniques can be applied either to extract parameters not easily obtained through LFN or to avoid the use of a specific setup. In this case, it could also be possible to extract trap density through capacitance curves, where a C-V meter is needed, or even through current curves (ID) as a function of time (t) or gate bias (VG). The ID-t and ID-VG characteristics can be an alternative to estimate active trap density and its profile along the bandgap, for example. Through a charge-pumping-like method, a pulsed signal can be applied in the gate of a transistor. Thus, the drain current will follow the gate bias, and the rise and fall times of ID can be associated with the occupation and release of traps, allowing for an estimation of Nit. It is worth mentioning that the accuracy of this estimation is better for devices with larger total trap density (N0) as stated in Fig. 3. Finally, there are methods that permit the extraction of active trap density and its profile along bandgap directly through ID-VG curves. In long devices, the active trap density can be estimated through the behavior of subthreshold swing, which is directly correlated to Nit and, in some ultimate devices, such as junctionless nanowire transistors, the variation of the substrate bias permits extraction of Nit profile along the bandgap (Fig. 4). This is only possible because, in these devices, the surface potential is not pinned at twice the Fermi potential in the conduction regime as it occurs in inversion mode transistors. Figure 1