Time-division-multiplexing using pulse position locking for 100 Gb/s applications

A bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.

Simultaneous measurement of the Henry factor of 14 longitudinal modes is implemented using a novel method based on sinusoidal phase modulation, without using any filter. Excellent agreement with fiber transfer function technique is achieved.

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate (BER) performance in high-speed (>40 Gb/s) data link systems. A 2.5 times 2.0-mm prototype chip is implemented in 0.18 -mum SiGe BiCMOS technology. The power consumption is 1.6 W with a +3.3-V supply voltage. Stable CDR operation with low-jitter performance (189 fs-rms) and the ADPC scheme using EOM feedback are demonstrated at 40 Gb/s. For a 30% duty-distorted 53 -mV signal, the proposed ADPC scheme drastically reduces the BER to le-12 compared to that (2e-7) without adaptive control. The experimental results demonstrate that the proposed CDR circuit greatly improves BER performance and provides robust CDR operation in high-speed data link systems.

Sinusoidal phase-modulating laser diode interferometer insensitive to the intensity modulation of the light source

A simplified algorithm for digital fringe analysis in two-wave interferometry with sinusoidal phase modulation

A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10 −12 . The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm 2 .

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs.

Input-data-independent clock and data recovery (CDR) employing bit-efficient braid clock signaling (BCS) for raw data transmission is presented for a point-to-point post-8K ultrahigh-definition (UHD) intrapanel interface at 24 Gb/s. The effect of input data pattern on CDR is analyzed, and the proposed bit-efficient BCS scheme for phase-locked loop (PLL)-based CDR eliminates the jitter-peaking dependency on the input data pattern. The removal of this dependency with the proposed BCS scheme decreases the loop filter size without jitter peaking and the bit error rate (BER). The prototype CDR has been fabricated using a 28-nm CMOS process and occupies an area of 0.024 mm2. The 24-Gb/s PLL-based CDR design with the BCS scheme consumes 13.4 mW. The CDR with BCS scheme achieves a recovered clock long-term jitter of 5.11 ps $_{\text{rms}}$ /37.5 ps $_{\text{p-p}}$ and a reduction in jitter peaking of 27 dB with a small-sized loop filter and six repeated consecutive identical digits in the stream of a PRBS7 pattern.

This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13μm CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17ps on 25−1 PRBS input pattern compared to 26ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3mW with the proposed BBPD.

In this paper, a clock and data recovery (CDR) based on digital phase interpolators using proportional-integral controller, PI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CDR, is proposed for GDDR5 interface trainings, i.e. read training and write training. The proposed CDR is composed of a deserializer, a phase detector, a programmable accumulator, a proportional-integral (PI) controller and four digital phase interpolators instead of two for the purpose of glitch free. Issues such as glitches during the phase switching and phase variation caused by different loads are discussed. Simulation results show that the proposed PI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CDR provides trade-off between low CDR jitter and low power consumption compared to modified and adaptive CDRs.

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CML buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit The area for the core circuits is 0.09 mm2, and the power consumption without output buffers is 96mW.

A 25-Gb/s low-power Clock and Data Recovery (CDR) with Clocked CMOS (C2MOS) D-Flip-Flop (D-FF) for low power operation is presented. In a CDR circuit, D-FF is one of the dominant factor on the power consumption. In this work, we design the low-power CDR with 25-GHz clock by using a C2MOS D-FF. C2MOS D-FF reduces the power by 84 % compared with a conventional current mode logic (CML) D-FF. To validate the proposed design, we fabricated 25-Gb/s CDR in a 65-nm CMOS process. The area for the core circuits is 0.047 mm2, and the power consumption without output buffers is 13 mW, which is 13 % of that for the conventional 65-nm CDR with 25-GHz clock.

We introduce a bit-error-rate (BER) estimation technique for high-speed serial links, which utilizes the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit in the receiver. In addition to offering insight into both the behavior of the CDR loop and the contribution of the jitter to the BER, the estimation technique can be used to accelerate the jitter tolerance test by eliminating the conventional BER measurement process. We will discuss two different versions of the estimation technique: one for use with linear CDR circuits and the other for non-linear CDR circuits. Experimental results comparing the estimated BER and the measured BER demonstrate the high accuracy of the proposed technique.

This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much lower speed. The CDR is able to track maximum frequency deviation of ±286.78 ppm between the incoming data and the local reference clock at 12.5Gb/s. The CDR occupies a chip area of 18700um2 and consumes 30.30mW of power at 12.5Gb/s.