Timing Error Tolerance in Pipeline Based Core Designs

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

Considering the problem that the timing synchronization calculation in high-speed remote sensing signal reception is complex and it is difficult for it to be parallel, this paper deduces and designs a parallel timing error estimation and correction scheme. This paper presents the design of polyphase DFT filter banks with non-maximum decimation. The feedforward timing error estimation and correction method is then improved to enhance synchronization performance. Finally, an implementation scheme for parallel timing error estimation and correction is proposed using the polyphase filter bank time domain decomposition method and the filter polyphase model. In the estimation module, the parallel implementation structure of the joint second-order and fourth-order cyclic statistics methods is designed, which improves the estimation accuracy. In the correction module, a fractional delay filtering method with higher accuracy is adopted in order to improve the calibration accuracy and reduce the computational complexity. The timing synchronization of a high-speed remote sensing signal with timing error is simulated and verified. The experimental results show that the parallel method proposed in this paper greatly reduces the processing speed of subband data, and has a good synchronization performance, which is close to the theoretical limit in the demodulation error rate. This paper utilizes a multi-phase DFT filter bank architecture to achieve parallel timing synchronization, which presents a novel approach for the future parallel reception of high-speed remote sensing signals.

Many satellite-based estimates use gauge information for bias correction. In general, bias-correction methods are focused on the intensity error and do not explicitly correct possible position or timing errors. However, position and timing errors in rainfall estimates can also lead to errors in the rainfall occurrence or the intensity. This is especially true for localized rainfall events such as the convective rainstorms occurring during the rainy season in sub-Saharan Africa. We investigated the use of warping to correct such errors. The goal was to gauge-adjust satellite-based estimates with respect to the position and the timing of the rain event, instead of its intensity. Warping is a field-deformation method that transforms an image into another one. We compared two methods, spatial warping focusing on the position errors and time warping for the timing errors. They were evaluated on two case studies: a synthetic rainfall event represented by an ellipse and a rain event in southern Ghana during the monsoon season. In both cases, the two warping methods reduced significantly the respective targeted (position or timing) errors. In the southern Ghana case, the average position error was decreased by about 45 km by the spatial warping and the average timing error was decreased from more than 1 h to 0.2 h by the time warping. Both warping methods also improved the continuous statistics on the intensity: the correlation went from 0.18 to at least 0.62 after warping in the southern Ghana case. The spatial warping seems more interesting because of its positive impact on both position and timing errors.

This letter presents a novel timing error detection and correction (EDaC) technique to reduce design margins in a near/sub-threshold RISCV-IM32 microprocessor. The proposed technique takes a snapshot of the datapath’s activity just before the launch of the next clock to determine if a timing error will occur. If so, it prevents the error at the last moment by gating the clock with one cycle. This avoids imposing additional hold constraints on the design and removes the need for a complex correction mechanism. The design is implemented in FDSOI 28 nm and achieves a margined minimum energy point (MEP) of 1.32 pJ/cycle at 3 MHz and 0.434 V. The EDaC technique robustly eliminates all voltage margin, resulting in an improved MEP of 0.92 pJ/cycle and 0.345 V at the same frequency.

This paper presents a timing error resilient flip-flop (ERFF) circuit with high energy-efficiency. The proposed flip-flop design automatically corrects timing errors and therefore minimizes the performance degradation due to variations. The simulation results show that the proposed design can achieve better energy-efficiency in ISCAS'89 benchmark circuits and LEON3 integer-processing unit, when compared to other state-of-the-art timing error detection and correction methods.

We propose a new timing error correction scheme for area-efficient design of flip-flop based pipeline. Key features in the proposed scheme are 1) one-cycle error correction using a new local stalling scheme and 2) selective replacement of the error detection and correction flip-flops in critical paths only. A 32-bit MIPS testchip in a 65 nm CMOS technology has been implemented as a testbed. By employing the proposed scheme in the flop-flop based pipeline, the area overhead due to the retiming process (∼21%) in the previous two-phase transparent latch based scheme can be eliminated. In addition, substantial area saving (16%) can be achieved compared to the state-of-the-art flip-flop based scheme thanks to the selective replacement of the error detection and correction flip-flops.

A new hybrid model for monthly runoff prediction using ELMAN neural network based on decomposition-integration structure with local error correction method

A local geometric error correction method is developed for a metrological scanning probe microscope. The method corrects geometric errors in stage displacements using the interferometric measurements of angular position and known geometric offsets. Local and global error correction methods are considered and general scaling dependences on the number of measured steps or points are derived and compared. For the local method, the total uncertainty scales the same or decreases with a sufficient number of measurement steps compared with the global method. Implementation of the local geometric error correction method is demonstrated on measurements of a three-dimensional height standard artefact. The applied error correction method reduces the contribution of geometric errors to the uncertainty budget by two orders of magnitude. The presented approach can be extended to any scanning technique where a measurement translation mechanism can be identified and accurately quantified by relating the measured values with a measurand.

This study assessed motor limits of regular tapping, timing error detection, and correction in 60 participants aged from 19 to 98 years. Rate limitations on motor production were estimated from the average inter-tap interval when tapping as fast as possible for 30 s. Timing error detection required participants to judge whether a sound sequence presented at a slow, intermediate, or fast speed contained an irregularity because of phase shift. This was performed with or without synchronizing to the sounds. On the basis of the just-detectable positive phase shift (JND), participants synchronized with sequences containing phase shifts that were subliminal, just detectable or supraliminal. On average, JNDs were 9% of the inter-onset interval and by and large were not affected by synchronization tapping. Speed of error correction was estimated from the number of tones to return within 20% of the preshift synchronization error. Consistent with previous findings of motor slowing with aging, the fastest inter-tap interval increased with age. However, there was no age-related decline in JNDs or speed of error correction, both of which reflect predictive abilities for intervals within the motor repertoire of human adults. These results point towards intact timing error processing up to an advanced age. In assessing timing abilities in the brain of older adults, it is important to differentiate between motor slowing and its impact on rhythmic behavior (e.g., walking pace) from anticipatory mechanisms ('what to expect when') and how these are used to adjust the timing of actions ('what to do when').

Low‐power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low‐power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time‐borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip‐flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two‐stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.

Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short path padding (hold time fixing) problem in resilient circuits is severer than conventional IC design. Therefore, in this paper, we focus on the short path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we propose coarse-grained and fine-grained padding allocation methods to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error resilient circuits.

Resilient circuits based on timing error detection and correction can mitigate the timing margin effectively, but usually at a cost of extra area overhead. One of the major sources of area overhead is short-path padding (hold time fix), which is much severer than in traditional IC design for near-threshold operation. Therefore, we propose an insertion methodology by using transmission gates to extend short-paths, which decreases area overhead than traditional resilient methods. Because the clock-controlled transmission gate (CTG) can extend all the short paths by half a clock when working as a transparent-low latch, the short-paths problem is solved. Besides, as the transmission gates synchronize the multiple short paths, it decreases the invalid flipping of combinational logic, which reduces the glitch power. Applied on a SHA-256 algorithm circuit in a 28nm CMOS process with 0.55V supply, the proposed technique reduces the area overhead a lot compared to the conventional short-path padding techniques. For combinational circuit, its area reduces from 153.34% to 4.43%, and for sequential circuit area, it reduces from 124.33% to 19.33%.

One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%–12% with a target throughput of 0.9 instructions per cycle, and 15%–18% when the target is 0.8.

Timing errors become dominant in dynamic performance of high-speed and high-resolution currentsteering Digital-to-Analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, a mapping technique, based on on-chip timing error measurement, was proposed. This mapping technique can significantly improve the dynamic performance, no matter if timing errors are interconnectionrelated or mismatch-related. Matlab simulation results show that the Spurious-free Dynamic Range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatchrelated timing errors.