Tools for the construction and analysis of systems

This special issue of Software Tools for Technology Transfer comprises extended versions of selected papers from the 26th edition of the International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2020). The focus of this conference series is tools and algorithms for the rigorous analysis of software and hardware systems, and the papers in this special cover the spectrum of current work in this field.

This volume contains the proceedings of the 4th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS 2006), held in Paris (France) on September 25-27, 2006. The aim of FORMATS is to promote the study of fundamental and practical aspects of timed systems, and to bring together researchers from different disciplines that share interests in modelling and analysis of timed systems.

A novel approach for software reliability analysis of digital instrumentation and control systems in nuclear power plants

Neural networks in economic analyses of wastewater systems

Computers and distributed software applications are becoming nowadays ubiquitous, and therefore their safety and reliability have increasingly important societal impact. In this context, formal methods equipped with powerful and versatile analysis tools are more important than ever in the design process. Despite the relevant scientific results and well-established tools obtained in recent years, there is a constant need of enhancing the analysis capabilities in order to handle increasingly complex systems. We briefly discuss some recent advances in the field, introducing five papers selected from the 22th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2016).

Tools that implement automated verification techniques can be used to fruitfully analyze and validate complex software systems. Developing such tools is an active research area that has produced several promising techniques in the last decade: however, many challenges lie ahead. We briefly review the research area and summarize four papers selected from the Eighteenth International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2012).

Several advances in fault tree models have been developed as an aid in the analysis of computer systems. Such advances include the ability to model sequence dependencies, the application of fault trees to the analysis of hardware and software fault tolerant systems, the ability to include details of the recovery process in the fault tree solution, and the use of modularization and binary decision diagrams as an aid in solution. In this paper we present a software package (DIFtree) that implements these advances into a single methodology that can solve both dynamic and static fault trees, and which is applicable to the analysis of hardware, software and humanware in complex computer-based systems.

Tools and Algorithms for the Construction and Analysis of Systems

PSGraph (Grov et al. in LPAR. Springer, Berlin, pp 324–339, 2013) is a graphical language to support the development and maintenance of proof tactics for interactive theorem provers. By using labelled hierarchical graphs this formalisation improves upon analysis and maintenance found in traditional tactic languages. Tool support for PSGraph is achieved by Tinker (Grov et al. in UITP 2014, ENTCS, vol 167. Open Publishing Association, London, pp 23–34, 2014; Lin et al. in Tools and algorithms for the construction and analysis of systems. Springer, Berlin, pp 573–579, 2016): a theorem prover-independent system, which is connected to several different provers, with a graphical user interface including novel features to develop and debug proof tactics graphically. In this paper we provide a detailed and formal account of PSGraph and show how theorem prover independence is achieved by Tinker. We then show practical use of PSGraph and Tinker by developing several proof patterns using the language and tool.

computer architecture; computer software selection and evaluation; formal logic; formal methods; model checker; model checking; multi core processors; program compilers; programming languages; semantics; software engineering; specifications; state space; verification

On the Use of Automata-based Techniques in Symbolic Model Checking: Invited Address

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We introduce FACT, a probabilistic model checker that computes confidence intervals for the evaluated properties of Markov chains with unknown transition probabilities when observations of these transitions are available. FACT is unaffected by the unquantified estimation errors generated by the use of point probability estimates, a common practice that limits the applicability of quantitative verification. As such, FACT can prevent invalid decisions in the construction and analysis of systems, and extends the applicability of quantitative verification to domains in which unknown estimation errors are unacceptable.

This paper reflects on the influential nature of some of the many scientific achievements linked to Ed Brinksma on the occasion of his 60th birthday. We in particular discuss pioneering contributions in the contexts of constraint-oriented specification, model-based testing, and cost-optimal timed reachability, as well as with respect to tools and algorithms for the construction and analysis of systems. We shed light on these achievements by linking a historical perspective with recent and very applied research directly rooted in these contributions.

Across the broad research field concerned with the analysis of computational systems, research endeavors are often categorized by the respective models under investigation. Algorithms and tools are usually developed for a specific model, hindering their applications to similar problems originating from other computational systems. A prominent example of such a situation is the area of formal verification and testing for hardware and software systems. The two research communities share common theoretical foundations and solving methods, including satisfiability, interpolation, and abstraction refinement. Nevertheless, it is often demanding for one community to benefit from the advancements of the other, as analyzers typically assume a particular input format. To bridge the gap between the hardware and software analysis, we propose Btor2C, a translator from word-level sequential circuits to C programs. We choose the Btor2 language as the input format for its simplicity and bit-precise semantics. It can be deemed as an intermediate representation tailored for analysis. Given a Btor2 circuit, Btor2C generates a behaviorally equivalent program in the language C, supported by many static program analyzers. We demonstrate the use cases of Btor2C by translating the benchmark set from the Hardware Model Checking Competitions into C programs and analyze them by tools from the Intl. Competitions on Software Verification and Testing. Our results show that software analyzers can complement hardware verifiers for enhanced quality assurance: For example, the software verifier VeriAbs with Btor2C as preprocessor found more bugs than the best hardware verifiers ABC and AVR in our experiment.