Towards Power Centric Analog Design

The growing appetite for in-memory computing is increasing memory's share of total server power consumption. However, memory power consumption in database management systems is not well understood. This paper presents an empirical characterization of memory power consumption in database systems, for both analytical and transactional workloads. Our results indicate that memory power optimization will be effective only if it can reduce back-ground power through more aggressive use of low power memory idle states.

Power consumption analysis of constant bit rate video transmission over 3G networks

On-site study was held to investigate the influences of load factor on power consumption and energy performance of water-cooled air conditioning (WCAC) system. A comprehensive measurement has been conducted to a WCAC plant of a supermall building located in West Java, Indonesia. Hourly and daily power consumption and performance characteristics of the WCAC system at varied load factors for a period of one year were evaluated. Regression analyses were developed to evaluate the influences of load factor on the WCAC power consumption and performance. The WCAC system was found to operate with varied load factor ranging from 70 percent to 100 percent. Power consumption of the system was strongly influenced by the load factor. Power consumption boosted when the power factor increased. The increase of load factor was also found to significantly improve the cooling capacity but reduce the coefficient of performance (COP). The best potential performance of the investigated WCAC system could be obtained at load factor between 70 percent and 85 percent.

Microelectronics mounted on a piezoelectric transducer: Method, simulations, and measurements

In this paper, we propose a method of using low-power small cameras to detect shelf status. For shopping malls, especially large shopping malls, when to replenish the shelves is very important. Whether they can replenish them immediately or not is directly related to their turnover. Now most shopping malls use manual inspection mode, that is, a waiter is responsible for certain shelves. They will replenish shelves in time when they are need. But this method wastes too much manpower. In our scheme, we use low-power IoT C ameras to M onitor S tore S helves (CMSS). Firstly, we put a specific photo on the back of the shelf and put the camera in front of the shelf to face the photo. When the goods on the shelf are emptied, the camera recognizes the graphics of the photos posted on the shelf in advance, and will send a message to inform the manager that replenishment is needed. For image recognition, we use an ultra low-power FPGA chip and run a convolutional neural networks(CNN) model on it to achieve. The chips and cameras we use are low power consumption. Their power consumption is milliwatts level, which is also the lowest power consumption device we know of running CNN. The power consumption of the entire system is less than 6 mW, and the price is about 22 dollars. Our experimental results show that on a shelf with a width of 40cm, the maximum lateral distance that the system can recognize is about 40cm. Compared with the existing solutions, our solution has the advantages of lower cost, low power consumption and easy maintenance.

Synergistic and interference effects in coaxial mixers: Numerical analysis of the power consumption

This paper describes a mixed-signal ECG processing platform with an 12-bit ADC architecture that can adapt its sampling rate according to the input signals rate of change. This enables the sampling of ECG signals with significantly reduced data rate without loss of information. The presented adaptive sampling scheme reduces the ADC power consumption, enables the processing of ECG signals with lower power consumption, and reduces the power consumption of the radio while streaming the ECG signals. The test results show that running a CWT-based R peak detection algorithm using the adaptively sampled ECG signals consumes only 45.6 μW and it leads to 36% less overall system power consumption.

Massive Multiple-Input Multiple-Output (Massive MIMO) serves as a foundational enabling technology for 5G and future communication systems, markedly boosting spectral and energy efficiency through the deployment of large-scale antenna arrays. However, the scaling-up of antenna arrays has led to a substantial increase in system power consumption and hardware costs, with high-precision analog-to-digital converters (ADCs) emerging as the dominant power consumption bottleneck in the radio frequency chain. To alleviate system complexity and power consumption, low-resolution ADCs (13 bits) have attracted extensive research interest in recent years. Such schemes can substantially curtail hardware costs and energy consumption while retaining satisfactory system performance. Nevertheless, the introduction of severe nonlinear distortion due to low-precision quantization disrupts the linear Gaussian model assumption upon which traditional receiver algorithms rely, resulting in compromised channel estimation and signal detection performance. Quantization errors demonstrate non-Gaussian and input-dependent characteristics, leading to the degradation of amplitude information and thus constraining the applicability of technologies such as high-order modulation and high-precision sensing. This paper presents a systematic review of low-precision quantization techniques for Massive MIMO. It first investigates the impacts of low-bit quantization on system models and signal statistical properties. Subsequently, it elaborates on transceiver architectures and key design challenges pertaining to low-precision ADCs/DACs. The paper highlights signal processing and algorithmic strategies to overcome quantization distortion, including Bussgang decomposition linearization methods, statistical inference techniques such as approximate message passing (AMP), model-driven deep learning frameworks, and quantization architectures endowed with noise-shaping capabilities. Finally, it discusses the challenges and future directions of this technology in emerging scenarios, including terahertz communications, intelligent reflecting surfaces, and integrated sensing and communication. This paper seeks to provide researchers with a systematic technical overview, clarifying the intrinsic connections and trade-offs among different methods, and offering valuable insights for the realization of high-energy-efficiency and low-cost Massive MIMO systems.

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. We study the trends of interconnect power consumption based on current and future technology node parameters. We show that 20%-30% of the power is consumed by interconnect resistance in optimally buffered global interconnect systems. We also study the analysis method based on a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is addressed. The theoretical results can be used for any kind of linear circuit, including RLC circuits.

Analysis of power consumption in standalone 5G network and enhancement in energy efficiency using a novel routing protocol

For analysis of power consumption of resistance spot welding systems field-circuit modelling is required. It includes both 2D eddy-current FEA analysis for estimation of the leakage impedance of transformer and P-Spice program for the circuit simulation. It is shown that the design of the transformer influences on the output current and power consumption. We used the equivalent circuit of three-winding transformer which differs from well-known equivalent circuit of such a transformer. This circuit is based on replacing the three-winding transformer with two two-winding transformers. The mutual impact of these transformers is modelled as a change of EMF on the terminals of their secondary windings by magnetic leakage fields. We investigated several transformer designs for the 7.5 kHz resistance spot welding system. Designs differ interleaving of primary and secondary windings and the number of primary winding coils. They have different leakage inductances and different coupling factors for the leakage flux. Calculations have shown that it is necessary to reduce the leakage inductances of transformers for increasing the operating current if output voltage is constant for all investigated transformers. On the bases of the investigations we developed transformer with the operating current 11 kA and frequency 7.5 kHz. It has almost twice less power consumption than the basic one. This result is confirmed experimentally.

Various gas pipeline networks used for the transit of energy sources are some of the most important infrastructures. However, carrying gas from one point to another is not the only concern when planning the construction of a new network or expanding an already existing one. The reliability and environmental impact of the system are crucial when evaluating the network and risks posed by potential gas leaks, fires, explosions, etc. Even though everyone admits that reliability is a key aspect of any system, its constraints will still be most likely neglected in the assessment of the pipeline project. How much energy is wasted by pushing an additional amount of gas through the pipeline network, which will eventually gush out of the pipeline because of one crack or another? Moreover, if this additional power or fuel consumption and related environmental impact are significant, how could it be reduced? In this paper, an approach is introduced for the simulation and quantification of how much more power would be required if the pipelines are regarded as unreliable (i.e., by leaking, rupturing, or even exploding). By employing stochastic simulations and time-dependent topology (topology determined by the value of a variable representing time) of the pipeline network as a case study for the selected representative gas transmission network, the amount of additional power consumption in gas compressor stations due to uncertain cracking and the leaking rate was evaluated. Although the analysis of power consumption was performed for a hypothetical network, the estimates of the cracking rates, detection effectiveness, and leaking rates used were as close to the real cases as possible.

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.

This report describes an experiment carried out to understand how traffic transfer affects power consumption on consumer-grade ADSL modems. Three ADSL modems were studied: a Linksys AG041, a Cisco 837 and a Netgear DG834G. Parallel streams of data were sent between a client and a server PC and the effect on power consumption by the routers was recorded. We discovered that there was almost no difference in the amount of power drawn from the routers with regards to the amount of data transferred or the duration of transfer. We did determine that the Linksys AG041 draws significantly more power than the other two routers.