Track Routing and Optimization for Yield

In this paper, we propose a track routing algorithm for timing and yield optimization. The algorithm solves the problem in two stages: wire ordering, and wire spacing and sizing. The wire ordering problem is solved by an algorithm based on wire merging. For the wire spacing and sizing problem, we show that it can be represented as a Mixed Linear Geometric Programming (MLGP) problem which can be transformed into a convex optimization problem. Since general nonlinear convex optimization may take a long running time, we propose a heuristic that solves the problem much faster. Experimental results show that, compared to the algorithm that only optimizes yield, our algorithm is able to improve the minimum timing slack by 20%.

In-line defect inspection is of crucial importance in controlling the quality of VLSI manufacturing processes. Wafer inspection tools such as KLA 21XX coupled with the review/classification stations, such as KLA25XX can be extremely effective in detecting problems in the processed batches of wafers. However, there is a need to properly allocate these machines among several process steps (levels) to maximize their utilization. Moreover, results of this in- line inspection such as defect distributions, both spatial and size, could be used to predict the yield impact of the detected defects. Up to now, the so-called 'kill ratios' were used to indicate the yield impact of defects per layer (e.g., polysilicon, metal1, metal2). The typical accuracy of 'kill ratio' based prediction was around 25%. In this paper, we demonstrate the methodology of yield impact prediction based on critical area concept. Critical area is extracted from the actual product layout by a software tool called MAPEX developed at CMU. The information about defect densities and size distributions is obtained from KLA inspection equipment. A prototype of a software system was developed that combines the information about the critical area with the defect size distributions, declustering of defect data into a yield model. This methodology and software system were verified on the experimental data from AMD Austin fabrication facility. The 'yield impact' prediction (equivalent to 'kill ratio' prediction) was performed for 7 different products ranging from SRAM to microprocessor to telecommunication products. The data was collected from more than 2000 wafers. The accuracy of our prediction was verified by comparing our functional yield estimate to the actual yield values from the probe testing measurements. We obtained an accuracy of 1% for the defects found by KLA in h polysilicon layer for dies affected by single defects only. Moreover, we were able to normalize the defect inspection data for the entire product family. This was possible due to the availability of information about critical area for each of the product. Hence, we were able to demonstrate the advantage of this methodology of determining the 'kill ratios' for the defect inspection data.

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.

The spectral p-norm and nuclear p-norm of matrices and tensors appear in various applications, albeit both are NP-hard to compute. The former sets a foundation of [Formula: see text]-sphere-constrained polynomial optimization problems, and the latter has been found in many rank minimization problems in machine learning. We study approximation algorithms of the tensor nuclear p-norm with an aim to establish the approximation bound matching the best one of its dual norm, the tensor spectral p-norm. Driven by the application of sphere covering to approximate both tensor spectral and nuclear norms ([Formula: see text]), we propose several types of hitting sets that approximately represent the [Formula: see text]-sphere with adjustable parameters for different levels of approximations and cardinalities, providing an independent toolbox for decision making on [Formula: see text]-spheres. Using the idea in robust optimization and second-order cone programming, we obtain the first polynomial-time algorithm with an [Formula: see text]-approximation bound for the computation of the matrix nuclear p-norm when [Formula: see text] is a rational, paving a way for applications in modeling with the matrix nuclear p-norm. These two new results enable us to propose various polynomial-time approximation algorithms for the computation of the tensor nuclear p-norm using tensor partitions, convex optimization, and duality theory, attaining the same approximation bound to the best one of the tensor spectral p-norms. Effective performance of the proposed algorithms for the tensor nuclear p-norm is shown by numerical implementations. We believe the ideas of [Formula: see text]-sphere covering with its applications in approximating nuclear p-norm would be useful for tackling optimization problems on other sets, such as the binary hypercube with its applications in graph theory and neural networks and the nonnegative sphere with its applications in copositive programming and nonnegative matrix factorization. Funding: This work was supported by the National Natural Science Foundation of China [Grants 71825003, 72394360, 72394364, 72171141, 72192830, and 72192832], and the program for Innovative Research Team of Shanghai University of Finance and Economics.

Due to the technology scaling down, process variation has become a crucial challenge on both interconnect delay and reliability. To handle the process variation, statistical optimization has emerged as a popular technique for yield improvement. As a relatively new technique, second-order conic programming (SOCP) has recently attracted very much attention in the literature for statistical circuit optimization. However, we observe significant limitations of SOCP in its flexibility, accuracy, and scalability for statistical circuit optimization, especially when interconnects are considered. We thus present in this paper an effective and efficient alternative for multi-constrained statistical circuit optimization by both gate and wire sizing using Lagrangian relaxation (LR). Compared with SOCP, experimental results show that our LRbased algorithm can achieve much better solution quality by reducing 21% area and obtain 560X speed-up over SOCP.

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.

This paper proposes an optimal day-ahead optimization schedule for gas-electric integrated energy system (IES) considering the bi-directional energy flow. The hourly topology of electric power system (EPS), natural gas system (NGS), energy hubs (EH) integrated power to gas (P2G) unit, are modeled to minimize the day-ahead operation cost of IES. Then, a second-order cone programming (SOCP) method is utilized to solve the optimization problem, which is actually a mixed integer nonconvex and nonlinear programming issue. Besides, cutting planes are added to ensure the exactness of the global optimal solution. Finally, simulation results demonstrate that the proposed optimization schedule can provide a safe, effective and economical day-ahead scheduling scheme for gas-electric IES.

A simple reliability model for the fatigue failure of repairable offshore structures

In this paper, linearly constrained and robust $\ell _{\infty }$ -norm beamforming techniques are proposed for non-Gaussian signals. A conventional approach for $\ell _{\infty }$ -minimization needs to solve a linear programming (LP) or second-order cone programming (SOCP). However, this strategy is computationally prohibitive for “big data” because the existing algorithms for LP or SOCP, such as simplex method or interior point method, can only solve small- or medium-scale problems. In this paper, the alternating direction method of multipliers (ADMM) is devised for large-scale $\ell _{\infty }$ -beamforming problems, where the core subproblems can be formulated concisely as a linearly or second-order cone constrained least squares and the proximity operator of the $\ell _{\infty }$ -norm in each iteration. Remarkably, a linear-time complexity algorithm is devised that efficiently computes the $\ell _{\infty }$ -norm proximity operator. Simulation results verify the high efficiency of the ADMM and the superiority of the $\ell _{\infty }$ -norm beamforming techniques over several representative beamformers, indicating that its performance can approach the optimal upper bound.

DC distribution systems, which can improve the accommodation of renewable energy sources and DC loads, have developed rapidly, leading to the appearance of hybrid AC/DC distribution systems. This paper proposes an optimal day-ahead scheduling model to increase the economy of the system operation considering the high penetration and uncertainty of the distributed generations. The proposed model aims to minimize the active power loss and electricity purchasing cost by coordinating active or reactive power outputs of voltage source converter (VSC), energy storage system (ESS) and static var compensation (SVC), as well as the voltage regulation capability of OLTC. Besides, the load model has been carefully analysed to implement conservation voltage reduction (CVR). In addition, VSC is detailed modelled to capture the coupling between active power and reactive power. Moreover, the second-order cone programming (SOCP) is used in this paper to transform the mixed integer nonlinear programming problem to a convex optimization one, which shortens the solving time. The IEEE 33-bus test system is employed to demonstrate the effectiveness and efficiency of the proposed method.

As VLSI circuits are scaled into advanced deep-submicron (DSM) dimensions, interconnection delay plays an important role for any performance-driven design. In general, the techniques of wire sizing and buffer insertion can be further used to reduce the timing delay of any interconnection net. Basically, the concept of uniform wire sizing cannot lead to the timing optimisation of any interconnection net. On the basis of the analysis of optimal wire width on one wire segment, the wire planning with optimal wire widths is proposed to use less routing area to reduce the timing delay of any interconnection net. Furthermore, given a compact floorplan with a set of interconnection nets, on the basis of the analysis of buffer locations on one wire segment and the construction of a recursive buffer-location graph, an area-driven buffer block planning with optimal wire sizing (ABBP_OWS) algorithm is proposed to insert the feasible buffers into the given floorplan for each net without destroying the timing constraint of any routing net, and the time complexity of the proposed ABBP_OWS algorithm is proved to be O(mn2), where m is the number of interconnection nets and n is the number of circuit blocks in the floorplan. Finally, the experimental results show that the proposed ABBP_OWS algorithm uses less routing area and floorplan area to meet more interconnection nets on all the tested benchmark circuits for interconnect-driven floorplanning.

A model for the cost/performance of a large-scale integrated circuit (LSI) is derived using critical area with 1/x/sup 3/ defect size distribution and common industry trends for device parameters and process parameters. The model predicts that dynamic random access memory bit cost will begin to increase sometime after 2005, if the current bit capacity increase rate of four times every three years remains effective. It is suggested that the rate is reduced to two times every two years, which will ensure a bit cost reduction beyond 2010. However, if the defect density can be reduced faster than the past trends, a four times bit capacity increase every three years can still remain cost effective.

This paper presents a method for rapidly generating controllability and reachability sets for constrained finite horizon Linear Time Varying (LTV) control systems by using convex optimization techniques. Set generation is accomplished by first solving a Semi-Definite Programming (SDP) problem and then solving a series of Second Order Cone Programming (SOCP) problems. Recent advances in convex optimization solvers have made it possible to find the solutions to these problems very quickly. From a geometric stand-point, we first find the largest volume symmetric simplex that fits within the constrained control problem, then grow new simplices out of the faces of the original simplex. This process is repeated until the growing polytope converges to the constraint boundaries of the actual set. Additionally, a method for incorporating stochastic constraints and uncertainties into the deterministic framework is developed by posing the stochastic constraints as chance-constrained constraints. Finally, the controllability set for a two-vehicle Low Earth Orbit (LEO) rendezvous problem with stochastic uncertainties is generated using the new algorithm.

This paper proposes a yield optimization method for standard cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield enhanced standard cells and the proposed method automatically creates yield enhanced cell layouts by decompacting the original cell layout using linear programming. We develop a novel accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints into linear programming. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the tradeoff curve of cell delay versus critical area and is used to create the yield enhanced cell library which is essential to realize yield-aware VLSI design flows.

In nowadays cloud computing systems, leveraging the virtualization technology, the customer's requested data computing or storing service is accommodated by a set of mutual-communicated Virtual Machines (VM) in a scalable and elastic manner. These VMs are placed in one or more datacenter nodes according to nodes' capacities, failure probabilities, etc. The VM placement availability refers to the probability that at least one set of the whole customer's requested VMs operates during the entire requested lifetime. The placed VMs should obey the agreed-upon availability, otherwise the cloud provider may face revenue loss. In this paper, we study the problem of placing at most H sets of k requested VMs on minimum number of datacenter nodes, such that the VM placement availability requirement is satisfied and each VM pair has a communication delay no greater than the specified. We prove that this problem is NP-hard. We subsequently propose an exact Integer Nonlinear Program (INLP) and an efficient heuristic to solve this problem. Finally, we conduct simulations to compare the proposed algorithms with two existing heuristics in terms of acceptance ratio, average number of used nodes and running time.