Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network

In this study commercial power VDMOS (Vertical Double Diffused MOS) transistors subjected to different stress conditions were investigated. Power VDMOS transistors are a type of power MOSFET designed for high-current and high-voltage applications. As shown in the technical documentation of the manufacturers, p-channel devices are usually designed to withstand currents of up to 6.8 A and drain-source voltages of – 100 V. Similar situation is for the n-channel devices, they exhibit comparable characteristics, with maximum current ratings of about 5.6 A and drain-source voltages of +100 V. These transistors are realized in standard polycrystalline silicon gate technology with hexagonal unit cell structure and approximately 100 nm thick gate oxide. Despite most of modern MOS transistors are realized with very thin gate oxide, expansion of power devices in various industrial, automotive applications, nuclear power plants, medical equipment and similar, has led to increased interest for investigations of reliability of power VDMOS transistors. For example, in specific situations they can be used for switching power supplies, DC\DC converters, voltage regulator modules, motor drive applications and so on. In most of these applications devices could be exposed to different stress conditions and, as a result, a shift in the threshold voltage is observed. So the degradation phenomena in these devices under different stress conditions (irradiation, high electric field, hot carriers injection, unclamped inductive switching, negative bias temperature instability (NBTI), NBTI under magnetic field, NBTI and irradiation, self-heating and so on) has been the subject of extensive research. A large number of researchers investigated the behavior of threshold voltage and analyzed the underlying changes of gate oxide-trapped charge and interface trap densities in power VDMOS devices subjected to different types of static and pulsed bias temperature stresses. Namely, this investigation is of great importance, bearing in mind that the electric fields and temperatures applied in NBT stressing can be approached to those achieved during the routine operation of power VDMOS devices in automotive and industrial applications. The responsible mechanisms that explain experimental data have not yet been fully explained. On the other hand, from the aspect of practical applications, it is necessary to know how the parameters of these devices change during the stress in order to be able to determine the lifetime. This is the main reason why several voltage and temperature lifetime models have been developed in the previous period. In order to investigate device lifetime of commercial p- and n-channel power VDMOS devices IRF9520 and IRF510, respectively, devices were stressed up to 168 hours by applying negative or positive gate voltages in the range 30 – 55 V, with drain and source terminals grounded, at temperatures ranging from 125 to 175 oC. The threshold voltage was used as a degradation monitor, which is widely accepted as a well-suited parameter in the literature. The use of different voltage and temperature models for extrapolation to typical operation voltage and temperature, respectively, were demonstrated. A new approach in estimating the device lifetime for arbitrary operating conditions that assumes multiple extrapolation along both voltage and temperature axes was demonstrated. A detailed analysis was performed to compare both chosen model and selected failure criterion. Keywords: VDMOS, degradation, NBTI, lifetime Acknowledgment: This work was supported by the Ministry of Science, Technological Development and Innovation of the Republic of Serbia [grant number 451-03-137/2025-03/200102]. Part of this work was supported by the L’Oréal-UNESCO project "Influence of Multiple Stress Factors on Components Integrated in Systems Intended for Use in Radiation Environments" and by the Horizon Europe Twinning project AIDA4Edge (Grant Agreement No. 101160293).

A comparative study is carried out to clarify the energy distribution of traps under hot carrier degradation (HCD) and negative bias temperature instability (NBTI) in short channel p-FinFETs. Two sources of traps, pre-existing traps and generated traps, are identified and their energy profiles are separated using Discharging-based Multi-pulse (DMP) method. The pre-existing traps are located below valance band of silicon (Ev), while the two generated traps are located in 0.4eV above E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> and near conduction band (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) of silicon, respectively. The two generated traps are highly sensitive to stress voltage and stress time under NBTI and HCD, however, the generated trap 1 is more sensitive to stress temperature than generated trap 2 under HCD. When switching to long channel devices, the overall degradation is reduced due to less trap generation.

Resonant rotary clocking is a low-power clocking technology for multi-phase clock generation in GHz frequency range. In this paper, Rotary Traveling Wave Oscillators (RTWOs) are analyzed under process variations and negative bias temperature instability (NBTI) at the 90nm technology node. The analysis is focused on 1) variations in the physical geometries of the rotary ring, 2) inter and intra-die transistor variations, 3) power supply fluctuation and 4) NBTI. Monte-Carlo based analysis are performed to study the effects of process variations and transistor aging on the operating frequency and power consumption of the rotary ring at a temperature of 110° C. SPICE based simulations show natural robustness against process variations, and NBTI.

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V TH transistors age faster than the high V TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V TH with technology scaling. Also NBTI effect is more significant at higher temperature.

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ V th and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ V th we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

Thermal management of Integration Circuit (IC) becomes more and more important with the scaling of CMOS technology and dramatic increase of power density. Performance of thermal management application is highly related to the accuracy of the temperature monitoring devices. However, due to increasing process variations and parameter drifts, temperature measurements by on-chip thermal sensors may not be accurate unless these sensors are calibrated before shipping the devices to the users. Existing calibration methods impose large time cost and cannot be used for in-field calibration. In this paper, we propose a technique to calibrate on-chip thermal sensors during manufacturing as well as in-field. We model the cyclic dependence between leakage power and temperature and perform calibrations to evaluate the calibration accuracy. Experimental results on 100 dies with different process variation parameters and three corner cases show that our technique have very high accuracy.

This paper presents a comprehensive study of the impact of Hot Carrier Injection (HCI) on differential LC Voltage Controlled Oscillator (VCO) reliability tests. Although Negative Bias Temperature Instability (NBTI) has been recognized as major cause for reliability degradation of advanced circuits, HCI-induced degradation may become significant due to the accelerated aging of reliability tests leading to incorrect circuit lifetime prediction. To distinguish HCI effects, different stress voltages and frequencies are applied in Constant Voltage Stress (CVS) and Ramp Voltage Stress (RVS) tests. It is verified that the stress voltage and frequency dependence of time and voltage exponents in the reliability tests are due to the effect of HCI. Based on the observed results, a methodology is proposed to define proper stress conditions for accelerated circuit reliability tests for better lifetime prediction.

We utilize magnetic resonance measurements to identify the fundamental atomic-scale defect structures involved in the negative bias temperature instability. In gate stacks composed of pure silicon dioxide, we find a degradation mechanism directly involving P b0 and P b1 defect centers (silicon dangling bond defects in which the silicon is back-bonded to three other silicon atoms precisely at the silicon/silicon dioxide interface). We observe that, in pure SiO2-based devices, the generation of these interface defects is catalyzed by the generation of E′ center bulk dielectric defects (silicon dangling bond defects in which the silicon is back-bonded to oxygen atoms). These observations are the first to indicate a prominent role for E′ centers in the negative bias temperature instability for pure silicon dioxide-based devices. In gate stacks composed of plasma-nitrided oxides, we identify a degradation mechanism which is dominated by the generation of a new defect center which we identify as a K N center. K N centers are silicon dangling bond defects in which the silicon is back-bonded to three nitrogen atoms with second-nearest neighbor atoms likely including oxygen. K N centers are located within the amorphous silicon oxy-nitride and electrically behave as both interface states as well as bulk dielectric defects (serve as both recombination and tunneling sites). In these plasma-nitrided gate stacks, the negative bias temperature instability does not involve the generation of P b0 , P b1 , or E′ centers. These collective observations provide a useful fundamental understanding with which to critically examine the current and future negative bias temperature instability framework.

Integrated Circuits age differently based on their operating conditions. A device that operates under high voltage or temperature stress ages faster. In many safety critical applications, such as in automotive systems, avionics and cyber-physical infrastructure, users would like to know the residual life of its components to ensure timely replacements. This motivates design of a residual-life meter (RLM). A residual-life meter may also prevent re-entry of recycled ICs from discarded systems into the supply chain as new parts - a problem that is deemed as a threat to critical infrastructure. Design of lifespan meter requires analytical models for predicting residual life of an IC based on its history of operating conditions. A major contribution of this paper is development of an analytical model for determining the residual life of an IC. There are a number of aging mechanisms that impact the lifetime of an IC such as oxide breakdown, hot electron effect, negative bias temperature instability, electromigration and others. While the proposed approach is general, for the purpose of illustration, in this study, we focus on residual life modeling based on Electromigration. The model relies on current temperature as input which is obtained from on-chip temperature sensor. This obviates any need for workload characterization. Next, this paper presents three alternative circuit implementations of the proposed residual-life meter. Results show that an RLM can be implemented at an area of ∼ 350µm2, and frequency of 3.3 GHz in CMOS 45nm technology. The RLM relies on non-volatile storage for data retention and is immune to power shut-offs. Prior aging sensors rely on sample size of single path, which is statistically insignificant. This work provides an alternative approach of analytical modeling, which is statistically comprehensive while retaining the simplicity of a single meter design.

Analyzed herein is the effect of different germanium (Ge) concentrations on negative bias temperature instability (NBTI) and channel hot carrier (CHC) degradations in high-performance Si1-xGex pMOSFETs. It is shown that higher concentrations result in less NBTI degradation due to the increased barrier height between the SiGe and high-k dielectric interface, but it causes greater CHC degradation due to the decreased channel bandgap with higher Ge concentrations. Therefore, the tradeoff between NBTI and HC degradations for different Ge concentrations should be considered when developing high-performance Si1-xGex pMOSFETs.

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.