TSV diagnostics by X-ray microscopy

Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the pre-existing void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5μm in diameter and 26 μm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

3D-interconnect: Visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy

We proposed a scheme of nondestructive inspection and simple inline estimation of profiles of copper-filled through-silicon vias by viewing with a nano-focus X-ray microscope with a resolution of 250nm and applying supervised machine learning method. Defects in Φ5µ×50µm copper-pillars were recognized and classified and at the same time estimation of profiles of voids in the copper-pillars was carried out in cases that the voids can be assumed rotationally symmetric. Results of experiments showed good matches in the classification and estimation of geometrical parameters of the profiles of the copper-pillars with and without voids gave a good correlation with results of cross-sectional focused ion beam microscope views.

Hybrid Wafer-Level Packaging for RF-MEMS and Optoelectronic Applications

The pre-bond through silicon via (TSV) probing tests and fault localization are important for yield assurance in 3D-SICs. This paper proposes an optimization algorithm to generate the preferable set of test sessions for pre-bond TSV probing tests. Test sessions generated by the optimization algorithm can not only get localization of faulty TSVs in TSV network, but also reduce test time and cost of the pre-bond TSV test. By using the proposed optimization algorithm, the reduction in pre-bond TSV test time is 10% for the pinpointing of four faulty TSVs in 13-TSV network and even 20.5% for one faulty TSV in 6-TSV network compared to the original one [4].

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via (TSV) with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab. for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance (RLGC) model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6&. on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6∼4.0 times higher bandwidth than the conventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.

The current trend in wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect referred to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 104∕cm2 or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks.

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and discrete Fourier transform method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

With the rapid development of three-dimensional integrated circuit packaging technology, through silicon via (TSV) has been used to bond the stacked chips. Cu-In Solid-Liquid Interdiffusion (SOLID) low temperature bonding is a promising process for TSV stacked chip interconnection. In this paper, shearing properties of Cu/In/Cu SOLID bonding joints was studied. A specific Cu-In solder joint was designed for the test. The samples used in shear test were bonded at two different temperatures, 260 °C and 360 °C, for three different time, including 40min, 160min and 360min, respectively. Scanning Electron Microscope(SEM) and Energy-dispersive X-ray(EDX) were used to observe the fractured morphologies after shear test. The results reveal that shear strength of Cu-In solder joints increases as bonding time prolonged for samples bonded at 260°C, while the strength of samples bonded at 360°C stay constant as the bonding time increases. Fracture observation after shear test showed that fracture mode of solder joints is brittle fracture. Cleavage fracture is mainly found in solder joints bonded at 260°C. There are many tongue-patterns found on the fracture of solder joints bonded at 260°C for 360 min. Cleavage fracture is preferred for solder joints bonded at 360°C for both 40 min and 160 min, found at Cu2In phase. Comparatively, for those bonded at 360°C for 360 min, both intergranular fracture and cleavage fracture were found.

Fault Modeling, Testing, and Repair for Chiplet Interconnects