An optimization algorithm for pre-bond TSV probing tests and fault localization

Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.

Through-silicon vias (TSVs) are essential for 3D integrated circuits (ICs) and advanced chiplet packaging. The semiconductor industry is transitioning toward 3D ICs, chiplets, and system-in-package (SiP) solutions due to the slowdown of Moore’s Law and limitations in conventional silicon scaling. In this paper, we propose an optimized TSV architecture for high-frequency transmission to enhance its suitability for 6G communication chips, and develop a comprehensive equivalent circuit model for fault-free and faulty TSVs. This model accounts for open-circuit and short-circuit fault conditions while considering the effects of higher frequencies, substrate type, doping concentration, and adjacent layers. At the physical level, the TSVs are simulated using the Ansys High-Frequency Structure Simulator (HFSS), and the equivalent circuits are designed using the Cadence Virtuoso tool. An experimental evaluation is also conducted to validate the physical design. We position the TSVs in a pattern of ground-signal-ground (G-S-G) to reduce the effective inductance of the signal TSV, thereby minimizing inductive reactance at ultra-high frequencies. Consequently, the reflection coefficient remains below -10 dB across the frequency range of 0.1 to 146.3 GHz. Furthermore, we compare simulation outcomes from HFSS and Cadence for both fault-free and faulty TSVs under varying operating conditions. Additionally, the parasitic circuit components are characterized through extensive theoretical derivations for in-depth circuit verification. Collectively, the rigorous analysis, experimental validation, and thorough investigation of the proposed design and its equivalent circuit demonstrate their potential for use in creating datasets for a fault prediction machine learning model.

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

Three dimensional integrated circuits (3D ICs) have been proposed as a solution for the limitation of microfabrication technology. However, through-silicon via (TSV), which connects two different dies vertically, may fail, and it can decrease the yield of 3D-ICs. A novel TSV repair architecture to repair defect TSVs is proposed in this paper. By shifting the corresponding signals of the faulty TSVs vertically and diagonally to the non-faulty TSVs, the proposed method maintains repair rate of TSV to 88.6% when there are 8 faulty TSVs. The hardware area of MUXs in proposed method is 193.6μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while that of the previous work is 245.8spl mu/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 297.9 spl mu/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores and reuse wires which connect pins to the same functional TSVs. Experimental results based on the MCNC benchmarks circuits demonstrate the feasibility and effectiveness of the DfT optimization methods.

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and discrete Fourier transform method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose a diagnostic method for TSV defects by using X-ray projection microscopy. By optimizing the image contrast of the X-ray projection micrographs in reference to its X-ray intensity histogram, we could obtain the small defect features in TSVs fast and non-destructively. Comparison between this X-ray observation and the destructive cross sectional observation agreed very well. We also extended the implementation of this X-ray microscope diagnostic method to 8-in. full wafer observation. We investigated the wafers with copper-filled TSVs with 80 µm and 20 µm diameters, and confirmed the feasibility of this method for an in-line process monitoring.

Fault Modeling, Testing, and Repair for Chiplet Interconnects

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.